Skip to main content

Full text of "westernDigital :: dataBooks :: wd1983catalog 01"

See other formats


WESTERN DIGITAL 

CORPORAT/ON 

WD1000 Winchester Disk Controller 



D 

o 

o 
o 




FEATURES 

BUILT-IN DATA SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION LOGIC 

DATA RATES UP TO 5 MBITS/SEC 

CONTROL FOR UP TO 4 DRIVES 

CONTROL FOR UP TO 8 R/W HEADS 

1024 CYLINDER ADDRESSING RANGE 

256 SECTOR ADDRESSING RANGE 

CRC GENERATION/VERIFICATION 

AUTOMATIC FORMATTING 

128, 256, OR 512 BYTES PER SECTOR (ROM 

SELECTABLE) 

UNLIMITED SECTOR INTERLEAVE CAPABILITY 

OVERLAP SEEK CAPABILITY 

IMPLIED SEEK ON ALL COMMANDS 

AUTOMATIC RETRIES ON ALL ERRORS 

AUTOMATIC RESTORE AND RE-SEEK ON SEEK 

ERROR 

8-BIT HOST INTERFACE 

0°C to 50°C OPERATION 



GENERAL DESCRIPTION 

The WD 1000 is a stand-alone, general purpose Winchester 
controller board designed to interface up to four Win- 
chester disk drives to a host processor. The drive signals 
are based upon the floppy look-alike interface available on 
the Shugart Associates' SA 1 000, the Seagate Technology 
ST506, the Quantum Q2000, and other compatible drives. 
All necessary buffers and receivers/drivers are included on 
the board to allow direct connection to the drive. Either a 34 
pin (5V4 1 ' drive) or 50 pin (8" drive) connector is provided, as 
well as four 20 pin data connectors. 

Communications to and from the host computer are made 
via a separate computer access port. This port consists 
mainly of an 8 bit bi-directional bus and appropriate control 
signals. All data to be written to or read from the disk, status 
information, and macro cammands are transferred via this 8 
bit bus. An on board sector buffer allows data transfers to 
the host computer independent of the actual data transfer 
rate of the drive. 

The WD 1000 is based upon a proprietary chip set, the 
WD1 100, specifically designed for Winchester Control. 



ORGANIZATION 

The WD1000 has seven on board connectors. These con- 
nectors consist of a power connector, host interface con- 
nector, drive control connector, and four high speed data 
cable connectors. 

The drive control cable is daisy-chained to each of the four 
drives. Although there is space for two drive control 
connectors, only one would normally be used for any 
particular configuration. 

The drive data connectors carry differential signals and are 
radially connected. Up to four drives can be accommo- 
dated by the WD1 000. 

The host interface connector provides interface signals 
that are compatible with most microprocessors and mini- 
computers. 

WD1100 

For those who want to design their own board around the 
WD1100 chip set, Western Digital can provide schematics, 
artwork, and programming information. Western Digital 
also has a complete staff of Applications Engineers to 
provide additional support. For further information please 
contact your local representative, or our main plant listed 
on page 8. 



13 






otwrt ctmrnoi latch i 







■*«r iv tit 






ADR 














MCUC 






niw 




„ 


„ 


•-^mSou 






I1M 


T1 


0>H» 1N1CLK 






AD It 








" 




Mia 






, 


C 




» 


MOO BAM ROM 


1 


IK Jit* 




W 










11!?] 




VI 


•-*> WHl 




»„. 


SIM 


« 


-*• Will IXflll INDEX) 




wc — « 


■' 


Yf 


t-t- «ni 







,r a i 



E?* 1 S*f 

!__/ warn i hi 



KMCTKMW 




Dl OMlo 

Pt 



WD1000 BLOCK DIAGRAM 



SPECIFICATIONS 

Encoding method: 
Cylinders per Head: 
Sectors per Track: 
Heads: 
Drive Selects: 
Step rate: 

Data Transfer Rate: 

Write Precomp Time: 
Sectoring: 
Host Interface: 
Drive Capability: 
Drive Cable Length: 
Host Cable Length: 
Power Requirements: 

Ambient Temperature 

Operating: 
Relative Humidity: 
MTBF: 
MTTR: 
Length: 
Width: 
Height: 
Mounting Centers: 



MFM 

Up to 1024 

Up to 256 (512 byte sec) 

8 

4 

10 uS to 7.5 mS 

(0.5 mS increments) 

4.34 Mbits/sec or 

5.000 Mbits/sec 

10 nanoseconds 

Soft 

8 Bit bi-directional bus 

10 "LS" Loads 

10 ft. (3 M) max. 

3 ft. (1 M) max. 

+ 5V ±5%, 3.0A Max. (2.5A 

typ.) -8 to -18V, 50 mA* 

0°Cto50°C(32Fto122F) 

20% to 80% 

10,000 POH 

30 minutes 

9.9 in. (24.9 cm) 

6.8 in. (17.1 cm) 

0.75 in. (1.9 cm) 

6.375 x 9.375 in. (16 x 23.6 cm) 



HOST INTERFACING 

The WD1 000 is designed to easily interface to most micro 
computers and mini-computers. All interfacing is done 
through the Host Interface Connector (J5). The interface is 
very similar to Western Digital's family of Floppy Disk 
Controllers. The only exception is the inclusion of the WAIT 
line. 

Waits 



The WAIT control line goes true whenever'either of the 
following are true: 

• The WD1000 is accessing data internally to send to the 
host during a read operation 

• The WD1000 has not accepted the data from the host 
during a write operation. 



The definition of the WAIT line is very simila r to th e WAIT 
signal found on many popular processors. WAIT is also 
similar to the REPLY signal on Western Digital and other 
processors. 



* Optional -V Supply Available. 



WAIT will not necessarily make a transition for each access 
to the WD 1 000. When the WD1 000 can return the requ ested 
data within 100 nS, there will be no transition of the WAIT 
line. This should be interpreted as an instant REPLY on 
Western Digital Processors. 



14 



If the WD1000 can not re turn the requested dat a with in 100 
nS, it will assert its WAIT line. The period of the WAIT signal 
will vary from 750 nS to 6 uS wi th 1.25 uS being about 
average. The period of the WAIT only approaches 6 uS 
during a read or write which happens immediately after a 
command is written to the command register. This means 
that longer waits may be encountered during the first read 
or write to any WD1000 register if that first read or write 
happens within approximately 6 uS of a command being 
issued. 



During the time that WAIT is asserted, the host system 
must hold all of its strobe and address lines stable. On 
write operations, the DAL lines must also be held stable. 



The user can modify the timing of the wait signal by select- 
ing a jumper. The WD1000 is shipped with a jumper (or 
trace) between E4 and E5. This enables waits as soon as 
the CS signal is asserted. This timing is a requirement for 
some processors a nd com patible with most. If the host 
system requires the WAIT signal to be asserted only when 
RE or WE are asserted in conjunction with CS, the trace at 
E4 and E5 should be cut and a jumper should be installed 
between E4 and E3. 

The Host Interface connector (J5) consists of an eight bit 
bi-directional bus, three bit address bus, and seven control 
lines. All commands, status, and data are transferred over 
this bus. See Table 1: 



O 

_k 

o 
o 
o 



HOST INTERFACE CONNECTOR 




TABLE 1 


SIGNAL GROUND 


SIGNAL PIN 


SIGNAL NAME 


DESCRIPTION 


2 


1 


DAL0 


8 bit bi-directional Data Access Lines. These lines 


4 


3 


DAL1 


remain in a high-impedance state whenever the CS line 


6 


5 


DAL2 


is inactive. 


8 


7 


DAL3 




10 


9 


DAL3 




12 


11 


DAL5 




14 


13 


DAL6 




16 


15 


DAL7 




18 


17 


A0 


These three Address Lines are used to select one of 


20 


19 


A1 


eight registers in the Task File. They must remain 


22 


21 


A2 


stable during all read and write operations. 


24 


23 


CS 




When Card Select is active along with RE or WE Data 








is read or written via the DAL bus. CS must make a 








transition for each byte read from or written to the task 








file. 










26 


25 


WE 


When Write Enable is active along with CS the host 
may write data to a selected register of the WD1000. 


28 


27 


RE 




When Read Enable is active along with CS the host 








may read data from a selected register of the WD1000. 


30 


29 




Upon receipt of a CS the WAIT line may go active. It 


WAIT 








returns to the inactive state when the DAL lines are 








valid on a read, or data has been accepted on a write. 


32 


31 


Not Connected 




34 


33 


-V 


Optional -V input from host supplies -8 to -15V to 
the on-board -5 Volt regulaton (VRI). This power input 
is also available on J6, pin 2. -V is not required if 
DC/DC convertor (PSI) is used. 


36 


35 


INTRQ 


The INTerrupt ReQuest Line is activated whenever a 
command has been completed. It is reset to the 
inactive state when the Status Register is read, or a 
new command is loaded via the DAL lines. 



15 



HOST INTERFACE CONNECTOR (Continued) 



O 

o 
o 

o 



SIGNAL GROUND 



SIGNAL PIN 



SIGNAL NAME 



DESCRIPTION 



38 



37 



DRQ 



40 



39 



41 
42 



43-50 



MR 



Not Connected 
Not Connected 



Note: Grounds 



The Data ReQuest line is activated whenever the sector 
buffer contains data to be read by the host, or is 
awaiting data to be loaded by the host. This line is 
reset whenever the Data Register is read from or 
written to. The DRQ line will continue to toggle until 
the buffer is exausted or until a write or read is per- 
formed on the Cylinder Low register. 



The Master Reset line initializes all internal logic on the 
logic on the WD1000. Sector Number, Cylinder Number 
and SDH are cleared, stepping rate is set to 7.5 mS, 
Write Precomp is set to cylinder 128 and Sector Count 
is set to 1. The DRQ line is reset and the INTRQ line 
is set. 



+ 5V 8 power pins for regulated +5 volts. This power 
input is also available on J6, pin 3. 



Even numbered pins (2-40) are to be used as 
grounds. Power ground is available on J6, pin 1. 



signal 



DRIVE CONTROL CONNECTORS 

The drive control connector is a (relatively) low speed bus 
that is daisy chain connected to each of the drives (up to 
four) in the system. To properly terminate each TTL level 
output signal from the WD1000, the last drive in the daisy 
chain should have a 220/330 ohm line termination resistor 
pack installed. All other drives should have no termination. 
See Tables 2 and 3: 



34 PIN DRIVE CONTROL CONNECTOR 



TABLE 2 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 


O 


RWC 


3 


4 





Head Select 2 


5 


6 


O 


Write Gate 


7 


8 


I 


Seek Complete 


9 


10 


I 


TROOO 


11 


12 


I 


Write Fault 


13 


14 


O 


Head Select O 


15 


16 




NC 


17 


18 





Head Select 1 


19 


20 


I 


Index 


21 


22 


I 


Ready 


23 


24 





Step 


25 


26 





Drive Select 1 


27 


28 





Drive Select 2 


29 


30 





Drive Select 3 


31 


32 





Drive Select 4 


33 


34 


O 


Direction In 



50 PIN DRIVE CONTROL CONNECTOR FOR SA1000 
TYPE INTERFACE TABLE 3 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 


O 


RWC 


3 


4 


O 


Head Select 2 


5 


6 




NC 


7 


8 


I 


Seek Complete 


9 


10 




NC 


11 
13 


12 
14 


O 


NC 


Head Select O 


15 
17 


16 
18 





NC 


Head Select 1 


19 


20 


I 


Index 


21 


22 


I 


Ready 


23 


24 




NC 


25 


26 


O 


Drive Select 1 


27 


28 


O 


Drive Select 2 


29 


30 





Drive Select 3 


31 


32 


O 


Drive Select 4 


33 


34 


O 


Direction In 


35 


36 


O 


Step 


37 


38 




NC 


39 


40 


O 


Write Gate 


41 


42 


I 


TROOO 


43 


44 


I 


Write Fault 


45 


46 




NC 


47 


48 




NC 


49 


50 




NC 



16 



DRIVE CONTROL SIGNAL DESCRIPTIONS 



RWC 



When the Reduce Write Current line is activated with write 
gate, a lower write current is used to compensate for great- 
er bit packing density on the inner cylinders. The RWC line 
is activated when the cylinder number is greater than or 
equal to four times the contents of the Write Precomp Reg- 
ister. This output is valid only during Write and Format 
commands. 



Write Gate 

This output signal allows data to be written on the disk. 



Seek Complete 

Informs the WD1000 that the head of the selected drive has 
reached the desired cylinder and has stabilized. Seek Com- 
plete is not checked after a SEEK command, thus allowing 
overlapped seeks. 



Track 000 

Indicates that the R/W heads are positioned on the outer- 
most cylinder. This line is sampled immediately before 
each step is issued. 



Write Fault 

Informs the WD1000 that some fault has occurred on the 
selected drive. The WD1000 will not execute commands 
when this signal is true. 



HS0HS2 



Head Select lines are used by the WD1000 to select a speci- 
fic R/W head on the selected drive. 



Index 



Is used to indicate the index point for synchronization dur- 
ing formatting and as a time out mechanism for retries. 
This signal should pulse once each rotation of the disk. 



Ready 

Informs the WD1000 that the desired drive is selected and 
that its motor is up to speed. The WD1000 will not execute 
commands unless this line is true. 



Step 



This line is pulsed once for each cylinder to be stepped. 
The direction of the step will be determined by the DIREC- 
TION line. The step pulse period is determined by the inter- 
nal stepping rate register during implied seek operations or 
explicitly during Seek and Restore commands. Durin g auto 
restore, the step pulse period is determined by the SEEK 
COMPLETE time from the drive. 



Direction In 



Determines the direction of motion of the R/W head when 
the step line is pulsed. A high on this line defines the direc- 
tion as out and a low defines direction as in. 



DS1DS4 

These four Drive Select lines are used to select one of four 
possible drives. 

DRIVE DATA CONNECTOR 

Four data connectors (J1-4) are provided for clock signals 
and data between the WD1000 and each drive. All lines as- 
sociated with the transfer of data between the drive and the 
WD1000 system are differential in nature and may not be 
multiplexed. The data connectors are 20 pin vertical 
headers on tenth-inch centers that mate with Burndy 
#FRS20BS. The cable used should be flat ribbon cable or 
twisted pair with a length of less than 10 feet. The cable 
pln-outs are per Table 4: 

DATA CONNECTIONS AND DESCRIPTIONS TABLE 4 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


2 


1 


I 


- Drive Selected 


4 


3 




NC 


6 


5 




NC 


8 


7 




NC 




9 


O 


+ Timing Clock 




10 


O 


- Timing Clock 


11 






GND 


12 






GND 




13 


O 


+ MFM Write Data 




14 


O 


- MFM Write Data 


15 






GND 


16 






GND 




17 


I 


+ MFM READ DATA 




18 


I 


- MFM READ DATA 


19 






GND 


20 






GND I 



DIFFERENTIAL DATA DRIVER/RECEIVER 



HIGH 
TRUE" 




AMDS8LS31 
or75110A 



NOTE: ANY RS 422 ~ 1 

ORIVERfRECEIVER PAIR Z»106O 

WILL INTERFACE FLAT RIBBON OR TWISTED PAIR 

MAX 10 FT. 



-L AM 




HIQH 
TRUE 



1. Op«nlorAMDWLS31(ST6M) 
Cloud lor 7S110A(SA10OO) 



POWER CONNECTOR 

A three pin molex connector (J6) is provided for power In- 
put to the board. The customer supplied mating connector 
housing is Molex 03-09-1032. The pln-outs are as shown In 
Table 5: 

TABLE 5 



PIN 


SIGNAL NAME 


1 
2 
3 


GROUND 

- 8 to - 15 V unregulated 

+ 5 V regulated 



17 



o 

O 
O 
O 



COMMANDS 

The WD1000 executes five easy to use macro commands. 
Most commands feature automatic 'implied' seek, which 
means the host system need not tell the WD1000 where the 
R/W heads of each drive are or when to move them. The 
controller automatically performs all needed retries on all 
errors encountered including data CRC errors. If the R/W 
head mis-positions, the WD1000 will automatically perform 
a restore and a re-seek. If the error is completely unre- 
coverable, the WD1000 will simulate a normal completion 
to simplify the host system's software. 

Commands are executed by loading the command byte 
into the Command Register while the controller is not 
busy. (Controller will not be busy if it has completed the 
previous command.) The task file must be loaded prior to 
issuing a command. No command will execute if the Seek 
Complete or Ready lines are false or if the Write Fault line 
is true. Normally it is not necessary to poll these signals 
before issuing a command. If the WD1000 receives a com- 
mand that is not defined in the following table, undefined 
results will occur. 

For ease of discussion, commands are divided into three 
types which are summarized in Table 6: TABLE 6 



TYPE 


COMMAND 


7 


6 


5 


BITS 
4 3 


2 


1 





I 


Restore 











1 r 3 


r2 


n 


rrj 


I 


Seek 





1 


1 


1 r 3 


r;> 


M 


TJ 


II 


Read Sector 








1 


D 











III 


Write Sector 








1 


1 











III 


Format Track 





1 





1 












rjj.ro — STEPPING RATE 



0000 = 10uS 


1000 = 4.0mS 


0001 = 0.5mS 


1001 = 4.5mS 


0010 = 1.0mS 


1010 = 5.0mS 


0011 = 1.5mS 


1011 = 5.5mS 


0100 = 2.0mS 


1100 = 6.0mS 


0101 = 2.5mS 


1101 = 6.5mS 


0110 = 3.0mS 


1110 = 7.0mS 


0111 = 3.5mS 


1111 = 7.5mS 



D = DMA Read Mode 

= Programmed I/O Mode 

1 = DMA Mode 

NOTE: 

The DMA bit is used to position INTRQ in relation to 
DRQs during the read sector command. If the DMA bit 
is reset (D = 0), the interrupt will occur before the first 
DRQ. This allows the programmed I/O host to intervene 
and transfer the data from the sector buffer. If the DMA 
bit is set (D = 1), then the interrupt will occur only after 
the system DMA controller has transferred the entire 
buffer of data. 



TYPE I COMMANDS 

These commands simply position the R/W heads of the se- 
lected drive. Both commands have explicit stepping rate 
fields. The lower four bits of these commands form the 
stepping rate. 

RESTORE 

The Restore command is used to calibrate the position of 
the R/W head on each drive by stepping the head outward 
until the TROOO line goes true. Upon receipt of the Restore 
command, the Busy bit in the Status Register is set. Cylin- 
der High and Cylinder Low Registers are cleared. The lower 
four bits of the command byte are stored in the stepping 
rate register for subse que nt implied s eeks. The state of 
Seek Complete, Ready and Write Fault are sampled, and if 
an error condition exists, the Aborted command bit in the 
Error Register is set, the Error bit in the Status Register is 
set, an interrupt is generated and the Busy bit is reset. 
If no errors are encountered thus far, the internal head posi- 
tion register for the selected drive is cleared. The TROOO 
line is sampled. If TROOO is true, an interrupt is generated 
and the Busy bit is reset. If TROOO is not true, stepping 
pulses at a rate determined by the stepping rate field are 
issued until the TROOO line is activated. When TROOO is acti- 
vated, the Busy bit is reset and an interrupt is issued. If the 
TROOO line is not activated within 1023 stepping pulses, the 
TROOO Error bit in the Error Register and the Error bit in the: 
Status Register are set, the Busy bit is reset and an in- 
terrupt is issued. 
SEEK 

The Seek command positions the R/W head to a certain cyl- 
inder. It is primarily used to start two or more concurrent 
seeks on drives that support buffered stepping. Upon re- 
ceipt of the Seek command, the Busy bit in the Status 
Register is set. The lower four bits of the command byte 
are stored in the stepping r ate register for subseq uent 
implied see ks. The state of Seek Complete, Ready and 
Write Fault are sampled, and if an error condition exists, 
the Aborted command bit in the Error Register is set, the 
Error bit in the Status Register is set, an interrupt is 
generated and the Busy bit is reset. 
If no errors are encountered thus far, the internal head posi- 
tion register for the selected drive is updated, the direction 
line is set to the proper direction and a step pulse is issued 
for each cylinder to be re ad and an interrupt is issued. Note 
that the Seek Complete line is not sampled after the Seek 
command, allowing multiple seek operations to be started 
using drives with buffered seek capability. 

TYPE II COMMANDS 

This type of command is characterized by a transfer of a 
block of data from the WD1000 buffer to the host. This com- 
mand has an implicit stepping rate as set by the last Re- 
store or Seek command. 

The Read Sector command is used to read a sector of data 
from the disk to the host computer. Upon receipt of the 
Read comma nd, the Busy bit i n the S tatu s register is set. 
The state of Seek Complete, Ready and Write Fault are 
sampled, and if an error condition exists, the Aborted 
Command bit in the Error Register is set, the Error bit in the 
Status Register is set, and a normal completion is 
simulated. 



18 



If no errors a re encountered s o far, a Seek command is exe- 
cuted. Th e Seek Complete line is sampled. If the Seek 
Complete line does not go true within 128 Index pulses, the 
Aborted command bit in the Error Register is set, the Error 
bit in the Status Register is set, and a normal completion is 
simulated. 

Once the head has settled over the desired cylinder, the 
WD1000 will attempt to read the sector. The WD1000 per- 
forms all retries necessary to recover the data during the 
read command. The controller attempts to read the desired 
sector up to 16 times. It will attempt a retry if it does not 
find an ID, if the ID of that sector has a bad CRC, if the Data 
Address Mark (DAM) couldn't be found or even if the data 
was actually read from the disk but incurred a data CRC 
error. 

Every time the controller encounters an error, it records the 
occurance of that error in an internal register. If, after 16 
retries, the controller was not able to get a match on the ID 
field, it assumes that the head was possibly mis-positioned 
and executes an auto-restore. During the auto-restore, the 
stepping rate is implied to be equal to the Seek Complete 
period. After the auto-restore has been successfully com- 
pleted, the controller re-seeks and attempts to read the 
sector once again. An auto-restore will be performed only 
once per read or write sector command. 
If the controller encounters a non-recoverable error, the 
controller examines its internal error history register. It then 
sets the bit in the Error Register of the highest severity 
error incurred. If the Data CRC Error bit is set, the data that 
last produced that error will be available in the sector 
buffer. The Error bit in the Status Register is set and a 
normal completion is simulated. 

TYPE III COMMANDS 

This type of command is characterized by a transfer of a 
block of data from the host to the WD1000 buffer. These 
commands have implicit stepping rates as set by the last 
Restore or Seek command. 

WRITE SECTOR 

The Write Sector command is used to write a sector of data 
from the host computer to the disk. Upon receipt of the 
Write command, the controller generates DRQs for each 
byte to be written to the buffer. (Note: It is recommended 
that programmed I/O transfers should take place as a block 
move without consulting the DRQ bit in the Status 
Register.) 

After all data has been sent to the sector buffer, the Busy 
bit in the Sta tus Register is set. The state of Seek Com- 
plete, Ready and Write Fault are sampled, and if an error 
condition exists, the Aborted command bit in the Error 
Register is set, the Error bit in the Status Register is set, an 
Interrupt is generated and the Busy bit is reset. 

If no errors are encountered so far, a Seek command i s exe- 
cuted. Th e Seek Complete line is sampled. If the Seek 
Complete line doesn't go true within 128 Index pulses, then 
the Aborted command bit in the Error Register is set, the 
Error bit in the Status Register is set, an Interrupt is 
generated and the Busy bit is reset. 
Once the head has settled over the desired cylinder, it will 
attempt to read the ID of the sector. The WD1000 performs 



all retries necessary to recover the ID during the write com- 
mand. The controller attempts to read the ID of the desired 
sector up to 16 times. It will attempt a retry if it doesn't find 
an ID or if the ID of that sector has a bad CRC. 
Every time the controller encounters an error, it records the 
occurrence of that error' in an internal register. If, after 16 
retries, the controller was not able to get a match on the ID 
field, it assumes that the head was possibly mis-positioned 
and executes an auto-restore. During the auto-restore, the 
stepping rate is implied to be equal to the Seek Complete 
period. After the auto-restore has been successfully com- 
pleted, the controller re-seeks and attempts to write the 
sector once again. 

If the controller encounters a non-recoverable error, the 
controller examines its internal error history register. It then 
sets the bit in the Error Register of the highest severity 
error incurred. The Error bit in the Status Register is set, an 
Interrupt is generated and the Busy bit is reset. 
If the proper sector is located, the sector buffer is written to 
the disk, an interrupt is generated and the Busy bit is reset. 

FORMAT TRACK 

The Format command is used for initializing the ID and 
data fields on a particular disk. Upon receipt of the Format 
command, the controller generates DRQs for each byte of 
the interleave table to be written to the buffer. In all cases, 
the number of bytes transferred to the buffer must cor- 
respond to the current sector size. 

After all data has been sent to the b uffer, the Busy b i t in the 
Stat us Register is set. The state of Seek Complete, Ready 
and Write Fault lines are sampled. If an error condition 
exists, the Aborted command bit in the Error Register is 
set, the Error bit in the Status Register is set, an interrupt is 
generated and the Busy bit is reset. 



-REPEATED N TIMES- 



ll 



1- 



-DATA FIELD 



I*-*] ZOO oS. MIN. INDEX PULSE 



NOTE: 

1) When MSB of head byte = 1 , bad block is detected. 

2) Write Gate turn-on is 3 bytes after the ID field's CRC bytes. 

3) Write Gate turn-off is 3 bytes after the Data Field's CRC 
bytes. 

4) 12 bytes of zeroes are re-written on a Data Field update. 

5) The 2 LSB's of the IDENT byte are used for Cylinder high 
These values are: 

FE = to 255 cylinders 
FF = 256 to 511 cylinders 
FC = 512 to 767 cylinders 
FD = 768 to 1023 cylinders 

6) GAP 4 values are: 

SECTOR LENGTH GAP 3 GAP 4 SECTOR COUNT 



128 


15 


356 


54 


256 


15 


352 


32 


512 


30 


800 


17 



If no errors are encountered so far, a Seek command is exe- 
cuted. No verification of track positioning accuracy is per- 
formed because the track may not have any ID fields 
present. After th e Seek operation has been performe d, the 
Seek Complete line is sampled. If the Seek Complete line is 
not asserted within 128 Index pulses, the Aborted com- 



19 



o 

O 
O 
O 



mand bit in the Error Register is set, an Interrupt is 
generated and the Busy bit is reset. 

Once the head has settled over the desired cylinder, the 
controller starts writing a pattern of 4E's until the index is 
encountered. Once the index is found, a number of ID 
fields and nulled data fields are written to the disk. The 
number of sectors written is equal to the contents of the 
Sector Count Register. As each sector is written, the Sector 
Count Register is decremented, and consequently, must 
be updated before each format operation. 

After the last sector is written, the controller back-fills the 
track with 4E's. When the next index pulse after the last 
sector is written is encountered, the format operation is ter- 
minated, an Interrupt is generated and the Busy bit is reset. 

SETTING UP TASK FILES 

Before any of the five commands may be executed, a set of 
parameter registers called the Task File must be set up. For 
most commands, this informs the WD1000 of the exact lo- 
cation on the disk that the transfer should take place. For a 
normal read or write sector operation, the Sector Number, 
the Size/Drive/Head, Cylinder Number, and Command 
registers (usually in that order) will be written. 

Note that most of these registers are readable as well as 
writable. These registers normally are not read from, but 
this feature is provided so that error reporting routines can 
determine physically where an error occurred without recal- 
culating the sector, head and cylinder parameters. 

Since the WD1000 can recall all the Task File parameters 
sent to it, it is recommended that Task File parameters be 
stored in the WD1000 as they are calculated. This will save 
the programmer a few instructions by not maintaining two 
copies of the same information. 

Since most hard disk drives contain more than one head 
per positioner, it is more efficient to step the R/W head as- 
semblies of most disk drives by cylinders, not tracks. In 
other words, the disk driver software should be designed to 
read or write all data that is directly accessable by all the 
heads on a positioner before stepping to a new cylinder. 

REGISTER SELECTION ARRAY 



CS 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


Deselected 


Deselected 















1 




1 




Data Register 
Error Register 
Sector Count 


Data Register 
Write Precomp 
Sector Count 








1 


1 


Sector Number 


Sector Number 







1 

1 
1 





1 




1 




Cylinder Low 
Cylinder High 
Size/Drive/Head 


Cylinder Low 
Cylinder High 
Size/Drive/Head 





1 


1 


1 


Status Register 


Command Register 



SDH REGISTOR 

BIT 

FUNCTION 



7 


6 5 


4 3 


2 1 





Sec 
Size 


Drive 
Select 


Head 
Select 



BIT 6 



BIT 5 



SECTOR SIZE 



256 Bytes 
512 Bytes 
128 Bytes 



BIT 4 



BIT 3 



DRIVE SELECTED 



Drive Sel 
Drive Sel 1 
Drive Sel 2 
Drive Sel 3 



BIT 2 








1 
1 
1 

1 



BIT1 



BITO 




1 


1 



1 



1 



HEAD SELECTED 



HeadO 
Headl 
Head 2 
Head 3 
Head 4 
Head 5 
Head 6 
Head 7 



STATUS AND ERROR REGISTER BITS 



BIT 


STATUS REGISTER 


ERROR REGISTER \. I 


7 


Busy 


'iBad Block Detect ! 


6 


Ready 


1CRC Error — Data Field 


5 


Write Fault 


, CRC Error— ID Field 


4 


Seek Complete 


ID Not Found 


3 


Data Request ' 


— 


2 


— 


Aborted Command 


T 


_». 


TROOO Error 


°! 


Error 


DAM not found 



PROGRAMMING 

Users familiar with floppy disk systems will find program- 
ming the WD1000 a pleasant surprise. A substantial 
amount of intelligence that was required by the host com- 
puter has been incorporated into the WD1000. The WD1000 
performs all needed retries, even on data CRC and heac 
positioning errors. Most commands feature automatic 
'implied' seek which means that seek commands need not 
be issued to perform basic read/write functions. The 
WD1000 keeps track of the position of up to four read' 
write head assemblies, so the host system does not haves 
to maintain track tables. All transfers to and from the disk 
are through an on-board full sector buffer. This means that 
data transfers are fully interruptable and can take place at 
any speed that is convenient to the system designer. In the 
event of an unrecoverable error, the WD1000 simulates a 
normal completion so that special error recovery software 
is not needed. 



See page 725 for ordering information. 



20 



Printed in U.S. A 



WESTERN DIGITAL 

CORPORAT/ON 

WD1001 Winchester Disk Controller 




/ ^m. ii 

^fes if 




GENERAL DESCRIPTION 

The WD 1001 is a stand-alone, general purpose 
Winchester controller board designed to interface up 
to four Winchester disk drives to a host processor. 
The drive signals are based upon the floppy look- 
alike interface available on the Shugart Associates' 
SA 1000, the Seagate Technology ST506, the Quan- 
tum Q2000, and other compatible drives. All neces- 
sary buffers and receivers/drivers are included on the 
board to allow direct connection to the drive. Either a 
34 pin (5 1 /4 " drive) or 50 pin (8" drive) connector is pro- 
vided, as well as four 20 pin data connectors. 

Communications to and from the host computer are 
made via a separate computer access port. This port 
consists mainly of an 8 bit bi-directional bus and ap- 
propriate control signals. All data to be written to or 
read from the disk, status information, and macro 
commands are transferred via this 8 bit bus. An on 
board sector buffer allows data transfers to the host 
computer independent of the actual data transfer rate 
of the drive. 

The WD1001 is based upon a proprietary chip series, 
the WD1100, specifically designed for Winchester 
Control. 



FEATURES 

SINGLE + 5V SUPPLY 

BUILT-IN DATA SEPARATOR 

BUILT-IN WRITE PRECOMPENSATION LOGIC 

DATA RATES UP TO 5 MBITS/SEC 

CONTROL FOR UP TO 4 DRIVES 

CONTROL FOR UP TO 8 R/W HEADS 

1024 CYLINDER ADDRESSING RANGE 

256 SECTOR ADDRESSING RANGE 

32 BIT ECC FOR BURST ERROR CORRECTION 

ERROR CORRECTION ON DATA FIELD 

ERRORS 

DIAGNOSTIC READS AND WRITES FOR 

CHECKING ERROR CORRECTION 

BAD BLOCK MAPPING CAPABILITY 

AUTOMATIC FORMATTING 

128, 256, OR 512 BYTES PER SECTOR 

(SOFTWARE SELECTABLE) 

UNLIMITED SECTOR INTERLEAVE CAPABILITY 

MULTIPLE SECTOR READS AND WRITES 

OVERLAP SEEK CAPABILITY 

IMPLIED SEEK ON ALL COMMANDS 

AUTOMATIC RETRIES ON ALL ERRORS 

AUTOMATIC RESTORE AND RE-SEEK ON 

SEEK ERROR 

8-BIT HOST INTERFACE 

0°C TO 50°C OPERATION 

ORGANIZATION 

The WD1001 has seven on-board connectors. These 
connectors consist of a power connector, host in- 
terface connector, drive control connector, and four 
high speed data cable connectors. 

The drive control cable is daisy-chained to each of 
the four drives. Although there is space for two drive 
control connectors, only one would normally be used 
for any particular configuration. 

The drive data connectors carry differential signals 
and are radially connected. Up to four drives can be 
accommodated by the WD1 001 . 

The host interface connector provides interface sig- 
nals that are compatible with most microprocessors 
and mini-computers. 

The WD1001 provides dual burst detection and single 
5-bit burst correction ECC circuitry. The ECC 
polynomial has been computer generated for op- 
timum error correction on Winchester Disks. 



a 

G) 

o 



21 



Y1 SUPPORT SIGNALS 








^ nh l 












rlOII 






8X300 
CPU 


10 
/ r - 


cc 


JNTROL I 




CONTROL 

S 

SUPPORT 

LOGIC 






16 








IT SIGNALS 




















>1 


I 










- / 




INST ROM 




»► CONTROL SIGNALS 




*/ 












»- TIMING SIGNALS 
















J7. J8 






INTERNAL BUS. 




DRIVE CONTROL 
LATCH 


11 


C 
O 
N 
T 
R 
O 
L 

P 
O 
R 
T 
S 










„ / 6 






"* / 














J5 










H 

S 
T 

I 
F 

c. 














WD1 10001 




W01 10003 








J1-J4 


> 


CONTROL 
LATCH 




512X8 
SECTOR 
SUFFER 


MEMORY 
ADDRESS 
REGISTER 






SERIAL- 
PARALLEL 
CONV 




AM DEI 




DATA 
SEPARATOR 


^ 


D 
R 

I 

V 
E 

D 
A 
T 
A 

P 
O 

R 
T 




*t-9 










— 












































8 


DATA 
LATCH 








PARALLEL 

SERIAL 

CONV. 






ECOCRC 
GEN/CHECKER 






MFM 






























3 


WD1 10005 




WD1 100-07 




WDimO-1P 




.*-/. DRQ. INTRQ, WAIT. 

SIMPLIFIED SYSTEM BLOCK DIAGRAM — WD1001 





SPECIFICATIONS 

Encoding method: 
Cylinders per Head: 
Sectors per Track: 
Heads: 

Drive Selects: 
Step rate: 

Data Transfer Rate: 

Write Precomp Time: 
Sectoring: 
Host Interface: 
Drive Capability: 
Drive Cable Length: 
Host Cable Length: 
Power Requirements: 

Ambient Temperature 

Operating: 
Relative Humidity: 
MTBF: 
MTTR: 
Length: 
Width: 
Height: 
Mounting Centers: 



MFM 

Up to 1024 

Up to 256 (512 byte sec) 

8 

4 

10 mS to 7.5 mS 

(0.5 mS increments) 

4.34 M bits/sec or 

5.000 Mbits/sec 

12 nanoseconds 

Soft 

8 Bit bi-directional bus 

10 "LS" Loads 

10 ft. (3M) max. 

3 ft. (1 M) max. 

+ 5V ±5%, 3.0A Max. (2.5A 

typ.) 

0°C to 50°C (32 F to 122 F) 

20% to 80% 

10,000 POH 

30 minutes 

9.9 in. (24.9 cm) 

6.8 in. (17.1 cm) 

0.75 in. (1.9 cm) 

6.375 x 9.375 in. 

(16x23.6 cm) 



HOST INTERFACING 

The WD1001 is designed to easily interface to most 
micro computers and mini-computers. All interfacing 
is done through the Host Interface Connector (J5). 
The interface is very similar to Western Digital's 
family of Floppy Disk Controllers. The only exception 
is the inclusion of the WAIT line. 

WAITS 



The WAIT control line goes true whenever either ol 
the following are true: 

• The WD1001 is accessing data internally to send 
to the host during a read operation. 

• The WD1001 has not accepted the data from the 
host during a write operation. 

The d efinition of the WAIT line is very similar to the 
WAIT signal found on many popular processors. 
WAIT is also similar to the REPLY signal on Western 
Digital and other processors. 



WAIT will not necessarily make a transition for each 
access to the WD1001. When the WD1001 can return 
the requested data w ithin 100 nS, there will be no 
transition of the WAIT line. This should be interpreted 
as an instant REPLY on Western Digital Processors. 

If the WD1001 cannot return the requested data 



22 



within 100 n S, it will assert its WAIT line. The period 
of the WAIT signal will vary from 750 nS to 6 u S with 
1.25 ^S being about average. The period of the WAIT 
only approaches 6 /uS during a read or write which 
happens immediately after a command is written to 
the command register. This means that longer waits 
may be encountered during the first read or write to 
any WD1001 register if that first read or write hap- 
pens within approximately 6 jjS of a command being 
issued. 



During the time that WAIT is asserted, the host sys- 
tem must hold all of its strobe and address lines sta- 
ble. On write operations, the DAL lines must also be 
held stable. 

The Host Interface connector (J5) consists of an 
eight bit bi-directional bus, three bit address bus, and 
seven control lines. All commands, status, and data 
are transferred over this bus. See Table 1: 






HOST INTERFACE CONNECTOR 



SIGNAL GROUND 



2 

4 

6 

8 

10 

12 

14 

16 



18 
20 
22 



24 



26 



28 



30 



32 



_34 
36" 



38 



SIGNAL PIN 



1 

3 

5 

7 

9 

11 

13 

15 



17 
19 
21 



23 



25 



27 



29 



31 



33 



35 



37 



SIGNAL NAME 



DAL0 
DAL1 
DAL2 
DAL3 
DAL4 
DAL5 
DAL6 
DAL7 



A0 
A1 
A2 



CS 



WE 



RE 



WAIT 



TABLE 1 



DESCRIPTION 



Not Connected 



Not Connected 



INTRQ 



DRQ 



8 bit bi-directional Data Access Lines. These 
lines remain in a high-impedance state when- 
ever the CS line is inactive. 



These three Address Lines are used to select 
one of eight registers in the Task File. They 
must remain stable during all read and write 
operations. 



When Card Select is active along with RE or 
WE, Data is read or written via the DAL bus. CS 
must make a transition for each byte read from 
or written to the task file. 



When Write Enable is active along with CS, the 
host may write data to a selected register of the 
WD1000. 



When Read Enable is active along with CS, the 
host may read data from a selected register of 
theWD1001. 



Upon receipt of a CS, the WAIT line may go ac- 
tive. It returns to the inactive state when the 
DAL lines are valid on a read, or data has been 
accepted on a write. 



The INTerrupt ReQuest Line is activated when- 
ever a command has been completed. It is reset 
to the inactive state when the Status Register is 
read, or a new command is loaded via the DAL 
lines. 



The Data ReQuest line is activated whenever 
the sector buffer contains data to be read by the 
host, or is awaiting data to be loaded by the 
host. This line is reset whenever the Data Regis- 
ter is read from or written to. The DRQ line will 
continue to toggle until the buffer is exhausted 
or until a write or read is performed on the 
Cylinder Low register. 



23 



HOST INTERFACE CONNECTOR 



TABLE 1 



3 

a 

_± 

o 

o 



SIGNAL GROUND 


SIGNAL PIN 


SIGNAL NAME 


DESCRIPTION 


40 


39 


MR 


The Master Reset line initializes all internal 
logic on the logic on the WD1001. Sector Num- 
ber, Cylinder Number and SDH are cleared, 
stepping rate is set to 7.5 mS, Write Precomp is 
set to cylinder 128 and Sector Count is set to 1. 
The DRQ and INTRQ lines are reset. 




41 


Not Connected 






42 


Not Connected 




43-50 


+ 5V 


8 power pins for regulated + 5 volts. This power 
input is also available on J6, pin 3. 


Note: Grounds 


All even numbered pins (2 through 40) are to be 
used as signal grounds. Power ground is avail- 
able on J6, pin 1. 



DRIVE CONTROL CONNECTORS 

The drive control connector is a (relatively) low speed 
bus that is daisy chain connected to each of the 
drives (up to four) in the system. To properly ter- 
minate each TTL level output signal from the 
WD1001, the last drive in the daisy chain should have 
a 220/330 ohm line termination resistor pack in- 
stalled. All other drives should have no termination. 
See Tables 2 and 3: 

34 PIN DRIVE CONTROL CONNECTOR TABLE 2 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 


O 


RWC 


3 


4 





Head Select 2 


5 


6 





Write Gate 


7 


8 


I 


Seek Complete 


9 


10 


I 


TR000 


11 


12 


I 


Write Fault 


13 


14 





Head Select O 


15 
17 


16 
18 


I 

O 


Sector 


Head Select 1 


19 


20 


I 


Index 


21 


22 


I 


Ready 


23 


24 





Step 


25 


26 


O 


Drive Select 1 


27 


28 





Drive Select 2 


29 


30 


O 


Drive Select 3 


31 


32 





Drive Select 4 


33 


34 





Direction In 



50 PIN DRIVE CONTROL CONNECTOR FOR 



SA1000 TYPE INTERFACE 



TABLE 3 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


1 


2 


O 


RWC 


3 


4 


O 


Head Select 2 


5 


6 




NC 


7 


8 


I 


Seek Complete 


9 


10 




NC 


11 


12 




NC 


13 


14 





Head Select O 


15 
17 


16 
18 


I 




Sector 


Head Select 1 


19 


20 


I 


Index 


21 


22 


I 


Ready 


23 


24 




NC 


25 


26 


O 


Drive Select 1 


27 


28 





Drive Select 2 


29 


30 


O 


Drive Select 3 


31 


32 





Drive Select 4 


33 


34 


O 


Direction In 


35 


36 





Step 


37 


38 




NC 


39 


40 


O 


Write Gate 


41 


42 


I 


TR000 


43 


44 


I 


Write Fault 


45 


46 




NC 


47 


48 




NC 


49 


50 




NC 



DRIVE CONTROL SIGNAL DESCRIPTIONS 
RWC 

When the Reduce Write Current line is activated with 
Write Gate, a lower write current is used to com- 
pensate for gre ater b it packing density on the inner 
cylinders. The RWC line is activated when the 
cylinder number is greater than or equal to four times 
the contents of the Write Precomp Register. This 
output is valid only during Write and Format com- 
mands. 



Write Gate 

This output signal allows data to be written on the 
disk. 



Seek Complete 

Informs the WD1001 that the head of the selected 
drive has reached the de sired cylinder and has 
stabilized. Seek Complete is not checked after a 
SEEK command, thus allowing overlapped seeks. 



24 



Track 000 

Indicates that the R/W heads are positioned on the 
outer-most cylinder. This line is sampled immediately 
before each step is issued. 



with a length of less than 10 feet. The cable pin-outs 
are per Table 4: 



3 



Write Fault 

Informs the WD1001 that some fault has occurred on 
the selected drive. The WD1001 will not execute 
commands when this signal is true. 

HS0HS2 

Head Select lines are used by the WD1001 to select a 
specific R/W head on the selected drive. 

index 

Is used to indicate the index point for synchroniza- 
tion during formatting and as a time out mechanism 
for retries. This signal should pulse once each rota- 
tion of the disk. 



DATA CONNECTIONS 
AND DESCRIPTIONS 



TABLE 4 



Ready 

Informs the WD1001 that the desired drive is selected 
and that its motor is up to speed. The WD1001 will 
not execute commands unless this line is true. 



SIGNAL 


SIGNAL 




SIGNAL 


GROUND 


PIN 


I/O 


NAME 


2 


1 


I 


- Drive Selected 


4 


3 




NC 


6 


5 




NC 


8 


7 




NC 




9 





+ Timing Clock 




10 





-Timing Clock 


11 






GND 


12 






GND 




13 





+ MFM Write Data 




14 





-MFM Write Data 


15 






GND 


16 






GND 




17 


I 


+ MFM Read Data 




18 


I 


- MFM Read Data 


19 






GND 


20 






GND 



Slep 

This line is pulsed once for each cylinder to be 
steppe d. The direct ion of the step will be determined 
by the DIRECTION IN line. The step pulse period is 
determined by the internal stepping rate register 
during implied seek operations or explicitly during 
Seek and Restore commands. During auto restore, 
the step pulse period is determined by the SEEK 
COMPLETE time from the drive. 



Direction In 

Determines the direction of motion of the R/W head 
when the step line is pulsed. A high on this line 
defines the direction as out and a low defines 
direction as in. 

DSl DS4 

These four Drive Select lines are used to select one 
of four possible drives. 



DRIVE DATA CONNECTOR 

Four data connectors (J 1-4) are provided for clock 
signals and data between the WD1001 and each 
drive. All lines associated with the transfer of data 
between the drive and the WD1001 system are dif- 
ferential in nature and may not be multiplexed. The 
data connectors are 20 pin vertical headers on tenth- 
inch centers that mate with Burndy #FRS20BS. The 
cable used should be flat ribbon cable or twisted pair 



DIFFERENTIAL DATA DRIVER/RECEIVER 



HIGH 
TRUE 




HIGH 
TRUE 



AMD 26LS31 
or 751 10A 



NOTE: ANY RS 422 
DRIVER/RECEIVER PAIR 
WILL INTERFACE 



V AMD 26LS32 



Z X = 105Q 

FLAT RIBBON OR TWISTED PAIR 

MAX 10 FT. 



POWER CONNECTOR 

A three pin molex connector (J6) is provided for 
power input to the board. The customer supplied 
mating connector housing is Molex 03-09-1032. The 
pin-outs are as shown in Table 5: 

TABLE 5 



PIN 



SIGNAL NAME 



Ground 

Not Connected 

+ 5 V Regulated 



25 



2 

o 
o 



COMMANDS 

The WD1001 executes five easy to use macro 
commands. Most commands feature automatic 
'implied' seek, which means the host system need 
not tell the WD1001 where the R/W heads of each 
drive are or when to move them. The controller 
automatically performs all needed retries on all 
errors encountered including data ECC errors. If the 
R/W head mis-positions, the WD1001 will automat- 
ically perform a restore and a re-seek. If the error is 
completely unrecoverable, the WD1001 will simulate 
a normal completion to simplify the host system's 
software. 

Commands are executed by loading the command 
byte into the Command Register while the controller 
is not busy. (Controller will not be busy if it has 
completed the previous command.) The task file 
must be loaded prior to issuing a command. No 
command will execute if the Seek Complete or 
Ready lines are false or if the Write Fault line is true. 
Normally it is not necessary to poll these signals 
before issuing a command. If the WD1001 receives a 
command that is not defined in the following table, 
undefined results will occur. 

For ease of discussion, commands are divided into 
three types which are summarized in Table 6: 



TABLE 6 



TYPE 


COMMAND 


7 6 


5 


BITS 

4 3 2 10 


II 
III 
III 


Restore 
Seek 

Read Sector 
Write Sector 
Format Track 



1 


1 




1 
1 
1 




1 r3 r2 n ro 
1 r3 r2 n ro 

D M L 

1 M L 
10 



rfrro - STEPPING RATE 





0000 = 10 M S 


1000 = 4.0mS 




0001 = 0.5mS 


1001 = 4.5mS 




0010 = 1.0mS 


1010 = 5.0mS 




0011 = 1.5mS 


1011 = 5.5mS 




0100 = 2.0mS 


1100 = 6.0mS 




0101 = 2.5mS 


1101 = 6.5mS 




0110 = 3.0mS 


1110 = 7.0mS 




0111 = 3.5mS 


1111 = 7.5mS 


D 


= DMA Read Mode 


L = Long Read/Write 





= Programmed I/O 






Mode 


= Normal Read/Write 


1 


= DMA Mode 


1 = Long Read/Write 



M = 1 = Multiple Sector Read/Write 
= Single Sector Read/Write 



NOTE: 

The DMA bit is used to position INTRQ in relation to 
DRQs during the read sector command. If the DMA 
bit is reset (D = 0), the interrupt will occur before the 
first DRQ. This allows the programmed I/O host to 
intervene and transfer the data from the sector buffer. 
If the DMA bit is set (D = 1), then the interrupt will 
occur only after the system DMA controller has 
transferred the entire buffer of data. 

TYPE I COMMANDS 

These commands simply position the R/W heads of 
the selected drive. Both commands have explicit 
stepping rate fields. The lower four bits of these 
commands form the stepping rate. 

RESTORE 

The Restore command is used to calibrate the 
position of the R/W head on each d rive by stepping 
the head outward until the TR000 line goes true. 
Upon receipt of the Restore command, the Busy bit 
in the Status Register is set. Cylinder High and 
Cylinder Low Registers are cleared. The lower four 
bits of the command byte are stored in the stepping 
rat e register for subsequen t im plied seeks. The state 
of Seek Complete, Ready and Write Fault are sam- 
pled, and if an error condition exists, the Aborted 
command bit in the Error Register is set, the Error bit 
in the Status Register is set, an interrupt is generated 
and the Busy bit is rest. 

If no errors are encountered thus far, the internal 
head positi on reg ister for the sele cted d rive is 
cleared. The TR000 line is sampled. If TR000 is true, 
an inte rrupt is generated and the Busy bit is reset. If 
TR000 is not true, stepping pulses at a rate deter- 
mined by the stepping rate fi eld are issued until the 
TR000 line is activated. When TR000 is activated, the 
Busy b it is reset and an interrupt is issued. If the 
TR000 line is no t activated within 1023 stepping 
pulses, the TR000 Error bit in the Error Register and 
the Error bit in the Status Register are set, the Busy 
bit is reset and an interrupt is issued. 

SEEK 

The Seek command positions the R/W head to a 
certain cylinder. It is primarily used to start two or 
more concurrent seeks on drives that support buf- 
fered stepping. Upon receipt of the Seek command, 
the Busy bit in the Status Register is set. The lower 
four bits of the command byte are stored in the 
stepping rat e regi s ter for subsequen t im plied seeks. 
The state of Seek Complete, Ready and Write Fault' 
are sampled, and if an error condition exists, the 
Aborted command bit in the Error Register is set, the 
Error bit in the Status Register is set, an interrupt is 
generated and the Busy bit is reset. 

If no errors are encountered thus far, the internal 
head position register for the selected drive is up- 
dated, the direction line is set to the proper direction 
and a step pulse is issued for each cylinder to be read 



26 



and an interrupt is issued. Note that the Seek 
Complete line is not sampled after the Seek com- 
mand, allowing multiple seek operations to be 
started using drives with buffered seek capability. 

TYPE II COMMANDS 

This type of command is characterized by a transfer 
of a block of data from the WD1001 buffer to the host. 
This command has an implicit stepping rate as set by 
the last Restore or Seek command. 

READ SECTOR 

The Read Sector command is used to read a sector of 
data from the disk to the host computer. Upon receipt 
of the Read command, the Busy bit in the Status 
regi ster is set. The state of Seek Complete, Ready 
and Write Fault are sampled, and if an error condition 
exists, the Aborted Command bit in the Error Regis- 
ter is set, the Error bit in the Status Register is set, 
and a normal completion is simulated. 

If no errors are en coun t ered so fa r, a Seek command 
is e xecut ed . The Se ek Complete line is sampled. If 
the Seek Complete line does not go true within 128 
Index pulses, the Aborted command bit in the Error 
Register is set, the Error bit in the Status Register is 
set, and a normal completion is simulated. 

Once the head has settled over the desired cylinder, 
the WD1001 will attempt to read the sector. The 
WD1001 performs all retries necessary to recover the 
data during the read command. The controller at- 
tempts to read the desired sector up to 16 times. It 
will attempt a retry if it does not find an ID, if the ID of 
that sector has a bad CRC or if the Data Address 
Mark (DAM) couldn't be found or even if the data was 
actually read from the disk but incurred an un- 
correctable error. 

Every time the controller encounters an error, it re- 
cords the occurrence of that error in an internal regis- 
ter. If, after 16 retries, the controller was not able to 
get a match on the ID field, it assumes that the head 
was possibly mis-positioned and executes an auto- 
restore. During the auto-rest ore, t h e stepping rate is 
implied to be equal to the Seek Complete period. 
After the auto-restore has been successfully com- 
pleted, the controller re-seeks and attempts to read 
the sector once again. An auto-restore will be per- 
formed only once per read or write sector command. 

If the WD1001 encounters an ECC error, it will at- 
tempt to correct the data in its sector buffer. If it can 
correct the data, the Corrected bit in the Status 
register will be set, if not, the Uncorrectable Error bit 
is set. 

If the controller encounters a non-recoverable error, 
the controller examines its internal error history 
register. It then sets the bit in the Error Register of 
the highest severity error incurred. If the Un- 
correctable bit is set, the data that last produced that 



error will be available in the sector buffer. The Error 
bit in the Status Register is set and a normal com- 
pletion is simulated. 

READ LONG 

This variation of the Read command allows the user 
to read the ECC check bits directly. The check bits 
are placed in the data buffer immediately behind the 
data. This increases the effective buffer length by 
four bytes. 

TYPE III COMMANDS 

This type of command is characterized by a transfer 
of a block of data from the host to the WD1001 buffer. 
These commands have implicit stepping rates as set 
by the last Restore or Seek command. 

WRITE SECTOR 

The Write Sector command is used to write a sector 
of data from the host computer to the disk. Upon 
receipt of the Write command, the controller 
generates DRQs for each byte to be written to the 
buffer. (Note: It is recommended that programmed 
I/O transfers should take place as a block move 
without consulting the DRQ bit in the Status 
Register.) 

After all data has been sent to the sector buffer, the 
Busy bit in the Status Regi ster is set. The state of 
Seek Complete, Ready and Write Fault are sampled, 
and if an error condition exists, the Aborted com- 
mand bit in the Error Register is set, the Error bit in 
the Status Register is set, an Interrupt is generated 
and the Busy bit is reset. 

If no errors are en coun t ered so fa r, a Seek command 
is e xecuted. The Se ek Complete line is sampled. If 
the Seek Complete line doesn't go true within 128 
Index pulses, then the Aborted command bit in the 
Error Register is set, the Error bit in the Status 
Register is set, an Interrupt is generated and the 
Busy bit is reset. 

Once the head has settled over the desired cylinder, 
it will attempt to read the ID of the sector. The 
WD1001 performs all retries necessary to recover the 
ID during the write command. The controller at- 
tempts to read the ID of the desired sector up to 16 
times. It will attempt a retry if it doesn't find an ID or if 
the ID of that sector has a bad CRC. 

Every time the controller encounters an error, it 
records the occurrence of that error in an internal 
register. If, after 16 retries, the controller was not able 
to get a match on the ID field, it assumes that the 
head was possibly mis-positioned and executes an 
auto-restore. During the auto-restor e, the stepping 
rate is implied to be equal to the Seek Complete 
period. After the auto-restore has been successfully 
completed, the controller re-seeks and attempts to 
write the sector once again. 



a 



27 



If the controller encounters a non-recoverable error, 
the controller examines its internal error history 
<; register. It then sets the bit in the Error Register of 
O the highest severity error incurred. The Error bit in the 
q Status Register is set, an Interrupt is generated and 
O the Busy bit is reset. 

If the proper sector is located, the sector buffer is 
written to the disk, an interrupt is generated and the 
Busy bit is reset. 

WRITE LONG 

This variation of the write command allows the user 
to introduce various error patterns to check correc- 
tion capability. The check bits follow the data in the 
sector buffer. This increases the effective buffer 
length by four bytes. 

FORMAT TRACK 

The Format command is used for initializing the ID 
and data fields on a particular disk. Upon receipt of 
the Format command, the controller generates DRQs 
for each byte of the interleave table to be written to 
the buffer. In all cases, the number of bytes trans- 
ferred to the buffer must correspond to the current 
sector size. 



After all data has been sent to the buffer, the Bu sy bit 
in the St a tus Re gist er is set. The state of Seek 
Complete, Ready and Write Fault lines are sampled. 
If an error condition exists, the Aborted command bit 
in the Error Register is set, the Error bit in the Status 
Register is set, an interrupt is generated and the 
Busy bit is reset. 

If no errors are encountered so far, a Seek command 
is executed. No verification of track positioning 
accuracy is performed because the track may not 
have any ID fields present. After t he Seek operation 
has been perf ormed , t he See k Complete line is 
sampled. If the Seek Complete line is not asserted 
within 128 Index pulses, the Aborted command bit in 
the Error Register is set, an Interrupt is generated and 
the Busy bit is reset. 

Once the head has settled over the desired cylinder, 
the controller starts writing a pattern of 4E's until the 
index is encountered. Once the index is found, a 
number of ID fields and nulled data fields are written 
to the disk. The number of sectors written is equal to 
the contents of the Sector Count Register. As each 
sectdr is written, the Sector Count Register is 
decremented, and consequently, must be updated 
before each format operation. 




14 BYTES 



(A1) 



(IDENT) 



CYL 
LOW 



SH 



SEC 



CRC 
-2- 



3B 
(ct>4>) 



12 

BYTES 

(*4>) 



(A1) 



(F8) 



DATA 
FIELD 



ECC 

-4- 



3 BYTES 



-IDFIELD- 



200 nS. MIN. INDEX PULSE WRITE GATE- 



DATA FIELD- 



NOTE: 

1) When MSB of head byte = 1 , bad block is detected. 

2) Write Gate turn-on is 3 bytes after the ID field's CRC bytes. 

3) Write Gate turn-off is 3 bytes after the Data Field's ECC or 
CRC bytes. 

4) 1 2 bytes of zeroes are re-written on a Data Field update. 

5) The 2 LSB's of the IDENT byte are used for Cylinder high 
These values are: 

FE = to 255 cylinders 
FF = 256 to 511 cylinders 
FC = 512 to 767 cylinders 
FD = 768 to 1023 cylinders 

6) GAP 3 values are: 



SECTOR LENGTH 


GAP 3 


128 
256 
512 


15 
15 
30 



28 



After the last sector is written, the controller back- 
fills the track with 4E's. When the next index pulse 
after the last sector is written is encountered, the for- 
mat operation is terminated, an Interrupt is generated 
and the Busy bit is reset. 

SETTING UP TASK FILES 

Before any of the five commands may be executed, a 
set of parameter registers called the Task File must 
be set up. For most commands, this informs the 
WD1001 of the exact location on the disk that the 
transfer should take place. For a normal read or write 
sector operation, the Sector Number, the Size/Drive/ 
Head, Cylinder Number, and Command registers 
(usually in that order) will be written. 

Note that most of these registers are readable as well 
as writable. These registers normally are not read 
from, but this feature is provided so that error report- 
ing routines can determine physically where an error 
occurred without recalculating the sector, head and 
cylinder parameters. 

Since the WD1001 can recall all the Task File 
parameters sent to it, it is recommended that Task 
File parameters be stored in the WD1001 as they are 
calculated. This will save the programmer a few 
instructions by not maintaining two copies of the 
same information. 

Since most hard disk drives contain more than one 
head per positioner, it is more efficient to step the 
R/W head assemblies of most disk drives by cylin- 
ders, not tracks. In other words, the disk driver 
software should be designed to read or write all data 
that is directly accessible by all the heads on a 
positioner before stepping to a new cylinder. 

REGISTER SELECTION ARRAY 



CS 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


Deselected 


Deselected 














Data Register 


Data Register 











1 


Error Register 


Write Precomp 








1 





Sector Count 


Sector Count 








1 


1 


Sector Number 


Sector Number 





1 








Cylinder Low 


Cylinder Low 





1 





1 


Cylinder High 


Cylinder High 





1 


1 





Size/Drive/head 


Size/Drive/head 





1 


1 


1 


Status Register 


Command 
Register 



SDH REGISTER 



BIT 


7 


6 5 


4 3 


2 1 


FUNCTION 


Sec 
Ext 


Sec 
Size 


Drive 
Select 


Head 
Select 



BIT 7 





1 



SECTOR EXTENSION 



Selects CRC for data field 
Selects ECC for data field 



BIT 6 


BIT 5 


SECTOR SIZE 




1 



1 
1 


256 Bytes 
512 Bytes 
128 Bytes 



o 

o 
o 



BIT 4 


BIT 3 


DRIVE SELECTED 




1 
1 



1 


1 


Drive Sel 
Drive Sel 1 
Drive Sel 2 
Drive Sel 3 



BIT 2 


BIT1 


BITO 


HEAD SELECTED 











HeadO 








1 


Head 1 





1 





Head 2 





1 


1 


Head 3 


1 








Head 4 


1 





1 


Head 5 


1 


1 





Head 6 


1 


1 


1 


Head 7 



STATUS AND ERROR REGISTER BITS 



BIT 


STATUS REGISTER 


ERROR REGISTER 


7 


Busy 


Bad Block Detect 


6 


Ready 


Uncorrectable 


5 


Write Fault 


CRC Error— ID Field 


4 


Seek Complete 


ID Not Found 


3 


Data Request 


— 


2 


Corrected 


Aborted Command 


1 


— 


TR000 Error 





Error 


DAM not found 



PROGRAMMING 

Users familiar with floppy disk systems will find 
programming the WD1001 a pleasant surprise. A 
substantial amount of intelligence that was 
required by the host computer has been in- 
corporated into the WD1001. The WD1001 performs 
all needed retries, even on data ECC and head 
positioning errors. Most commands feature 
automatic 'implied' seek which means that seek 
commands need not be issued to perform basic 
read/write functions. The WD1001 keeps track of 
the position of up to four read/write head 
assemblies, so the host system does not have to 
maintain track tables. All transfers to and from the 
disk are through an on-board full sector buffer. This 
means that data transfers are fully interruptable and 
can take place at any speed that is convenient to 
the system designer. In the event of an 
unrecoverable error, the WD1001 simulates a 
normal completion so that special error recovery 
software is not needed. 



See page 725 for ordering information. 



29 



g 

o 
o 



This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is completed. 

Information furnished by Western: Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to changu 
specifications at anytime without notice. 



nn Printed in USA 



WESTERN DiGITAL 

CORPORATION 

WD1002 Winchester Disk Controller 




o 
o 
to 



GENERAL DESCRIPTION 

The WD1002 is next generation of Winchester 
Controllers. It utilizes the WD1010 Winchester 
controller chip, and provides for floppy disk back up 
using the WD279X series of single chip floppy 
controllers. 

Incorporated in this controller is all the circuitry 
needed for Hard disk control with floppy backup. 

The firmware is incorporated in the WD1010 and the 
controller is compatible with previous WD1000 and 
WD1001. Additional software is needed for the floppy 
disk backup. Users of the WD10007WD1001 need not 
use the floppy controller. 



FEATURES 

SINGLE 5V SUPPLY 
FLOPPY DISK BACKUP 
ECC/CRC 

ST506 OR SA1000 INTERFACE 
COMPACT SIZE 
SECTOR SIZES TO 1024 
DATA RATES TO 5MBS 
AUTOMATIC FORMATTING 
WD1000 COMPATIBILITY 

See page 725 for ordering information. 



31 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility Is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to chango 
specifications at anytime without notice. 



nn Printed in USA 



WESTERN DIGITAL 

CORPORATION 

WD1 100 Series Winchester Controller Chips 



DESCRIPTION 

The WD1100 Chip series provides a low cost alternative for 
developing a Winchester Controller. These devices have 
been designed to read and convert an MFM data stream 
into 8-bit parallel bytes. During a write operation, parallel 
data is converted back into MFM to be written on the disk. 
Address Marks are generated and detected while CRC 
bytes can be appended and checked on the data stream. 
The WD1100 is fabricated in N-channel silicon gate technol- 
ogy and is available in a 20-pin Dual-ln-Line package. 



WD110O01 SER/PARALLEL CONVERTER 

WD1 100-02 MFM GENERATOR 

WD1100-12 IMPROVED MFM GENERATOR 

WD1 100-03 AM DETECTOR 

WD1100-04 CRC GENERATOR/CHECKER 

WD1 100-05 PAR/SERIAL CONVERTER 

WD1 100-06 ECC/CRC LOGIC 

WD1100-07 HOST INTERFACE LOGIC 

WD1 100-09 DATA SEPARATION SUPPORT LOGIC 



FEATURES 

• SA1000/ST506 COMPATIBLE 

• SINGLE 5V SUPPLY 

• TRI-STATE DATA LINES 

• 5 MBITS/SEC TRANSFER RATE 

• SIMPLIFIED INTERCONNECT 

APPLICATIONS 

Winchester Controllers For: 

• SHUGART ASSOCIATES 

• SEAGATE TECHNOLOGY 

• QUANTUM CORP. 

• TANDON MAGNETICS 

• MINISCRIBE 

• RMS 

• CMI . . . AND OTHERS 



g 
§ 




WD1 100-01 

SERIAL/PARALLEL 
CONVERTER 



NRZ 


LZ 


SKPEN 


LZ 


WCLK 


LZ 


WCLK 


LZ 


RWC 


LZ 


CS 


tz 

lz 
lz 


DROCLK 


INTCLK 


NC 


lz 


vssfZ 



Zv cc 

Z MR 
Z] MFM 

ZJ iNTRQ 
23 DRQ 

23 EARLY 
~ ) LATE 
— I NOM 



WD1 100-02 

MFM GENERATOR 



NRZ CI 
SKPEN (Z 

wclk lz 

WCTRTZ 

rwc rz 



DRQCLK LZ 7 



INTCLK |Z 8 

2XDR (Z 9 

v S sC ,c 



Z v cc 

Z| A0 
ZiA1 

ZImR 

Zl MFM 
ZI INtRQ 
Z5RS 
ZI EARLY 
Zl LATE 
ZI NOM 



WD1100-12 

IMPROVED MFM GENERATOR 




Zl v CC 

Z] RST 

23 cp 
23 nc 

Zl AMDET 

Zl AMDET 

Zl QOUT 

ZJ N C 

Zl DCLK 

ZJ TEST 2 



WD1 100-03 

AM DETECTOR 



DIN 


LZ 




DOCK 


LZ 
LZ 


2 


SHFCLK 


3 


NC 


LZ 


i 


NC 


LZ 


5 


CWE 


LZ 


6 


DOCE 


LZ 




CRCIZ 


LZ 


8 


NC 


LZ 


9 


v S s 


c 


K 




WD1 100-04 

CRC GENERATOR/CHECKER 



Dorz 


1 20 


Zl v cc 


■"LZ 


2 19 


Z] EN 


D2 rz 


3 18 


Z| NC 


D3 rz 


4 17 


Z| TEST 


D4 rz 


5 16 


Zl BOONE 


D5 fZ 


6 15 


Z| DOUT 


D6 rz 


7 11 


23 SHFCLK 


07 C 


8 13 

9 12 


ZI~D 


"CLK |Z 


| WCLK 


v s S q 


10 11 


ZJ DCLK 



WD1 10005 

PARALLEL/SERIAL 
CONVERTER 



R/W fZ 

RCP [Z 

wcp rz 

RDAT I 

WDAT fZ 

SEL [Z 

ECCIZ LZ 

NC LZ 

ECCEN LZ 

VSS LZ 



20 


Zl 


vcc 


19 


p 


WBs" 


18 


Zl 


RBS 


17 


Zi 

z 


DCSS 


lb 


EDOUT 


15 


Zl 


SoTJf 


14 


z 


FBD 


13 


z 


cs"£" 


12 


z 


BS 


11 


Zl 


RWCP 



WD110006 

ECC/CRC 
LOGIC 



H0S LZ 

WR6 LZ 

RESET LZ 

CSAEN LZ 

AMDET LZ 

timclk lz 
rclkLZ 

INDEX Z. 

wraLZ 
VssLZ 



z 
z 
z 
z 
z 
z 

z 
z 



vcc 

WCLK 
5S 

waEn 

MODE 
RBS 
AMOUT 
CSAC 



WATT 
LINDEX 



WD1 10007 

HOST INTERFACE 
LOGIC 



33 






o 

o 



i \+ 


1.020 


T 1"* IV1AA 


"fWf 


TO 


OOTYP-^j [*- 1 


.035 
014 -055 


-*H 


.021 




.310 
MAX 



:^k T 



.295 



i 



1.040 
"MAX " 



.015 MIN 

->1 




.100 TYP 



T 



,! 



f 



.120 
MIN 



.035 
.055 



|-7T -J 



.320 
MAX 



.340 
.390 



L- 



20 LEAD CERAMIC "U" 

See page 725 for ordering information. 



20 LEAD PLASTIC 'V" 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



34 



Printed in USA 



Western Digital 

WD1 100-01 Serial/Parallel Converter 



DESCRIPTION 

The WD1 100-01 Serial/Parallel Converter allows the user to 
convert NRZ (non-return to zero) data from a Winchester 
disk drive into 8 bit parallel form. Additional inputs are pro- 
vided to signal the start of the parallel process, as well as 
Byte Strobes to signify the end of the conversion. The 
device contains two sets of 8-bit registers; one register may 
be read (in parallel), while data is being shifted into the 
other register. This double-buffering allows the Host to read 
data from the disk drive at one-eighth the actual data rate. 



g 
§ 



The WD1 100-01 is implemented in NMOS silicon gate 
technology and is available in a 20 pin plastic or ceramic 
dual-in-line package. 

FEATURES 

• SINGLE + 5V SUPPLY 

• DOUBLE BUFFERING 

• BYTE STROBE OUTPUTS 

• 5MBITS/SEC SHIFT RATE 

• SERIAL IN/SERIAL-PARALLEL OUT 

• 20 PIN DIP PACKAGE 



CLK £2 

NC LZ 



BCLR | 

TEST | 
D00C 
D01 £2 

D02 r~ 

D03 (Z 

D04Q 

VssC 



"V^r 



Zl v cc 

] EN 
] NRZ 
PST 
] DOUT 
| BDONE 



] SHFCLK 
] D07 

I D06 

| D05 



ST >— 
+5V 



TEST *- 



NRZ >- 



CLK *- 



+5V 



8 

Bit 
Counter 



cp 



D Q 

> LATCH 

R 



£> 



-*► BDONE 



8 Bit 
Shift Register 






-< EN 



■M BCLR 



DOUT 



SHFCLK 



cp 



8 Bit Register 



v t t t t t t '' 

D00 D01 D02 D03 D04 D05 D06 D07 



WD1 100-01 
Figure 1. Pin Connections 



WD1 100-01 
Figure 2. Block Diagrams 



35 






o 
o 



PIN 
NUMBER 


SYMBOL 


NAME 


FUNCTION 


1 


CLK 


CLOCK 


NRZ data is entered into the 8-bit shift register on the low- 
to-high transition of clock. 


2 
3 

4 


NC 


NO CONNECTION 


No connection. This pin is to be left open by the user. 

When this line is at a logic 0, the BDONE (Pin 15) line is held 
reset. 

This pin must be left open by the user. 


BCLR 
TEST 


BYTE CLEAR 


TEST INPUT 


5-9, 
11-13 


D00-D07 


DATA0-DATA7 


8 bit parallel data outputs. 


10 

14 


vss 

SHFCLK 


GROUND 


Ground. 

Inverted copy of CLOCK (pin 1) which is active when EN 
(pin 19) is at a logic 1. 


SHIFT CLOCK 


15 


BDONE 


BYTE DONE 


This signal is forced to a logic 1 signifying 8 bits of data 
have been assembled. BDONE remains in a logic 1 state 
until reset by a logic on the BCLR (pin 3) line. 


16 
17 


DOUT 
ST 


DATA OUT 


Serial Data Output from the 8th stage of the internal shift 
register. DOUT is in a high impedance state whenever EN 
(pin 19) is at a logic 0. 

This line enables the byte counter and is used for syn- 
chronization. It must be held to a logic 1 prior to first data 
bit on the NRZ (Pin 18) line. 


START 


18 
19 


NRZ 
EN 


NRZ DATA 
ENABLE 


NRZ serial data is entered on this pin and clocked by the 
low to high transition of CLK (pin 1). 


When this signal is at a logic 0, DOUT, SHFCLK, and 
BDONE outputs are in a high impedance state. 


20 


vcc 


vcc 


+ 5V ± 10% power supply input. 



DEVICE DESCRIPTION 

Prior to shifting data through the device, the WD1 100-01 
must be synchronized to the data stream. The ST line (Pin 
17 high) is used to hold the internal bit counter in a cleared 
state_until valid data (NRZ) and clocks (CLK) are entered. 
The ST line is a synchronous input and therefore requires 
one full[cycle of the CLK line (Pin 1) to occur in order to ac- 
cept a ST condition. After this happens, the device is ready 
to perform serial to parallel conversions. 

Data is entered on the NRZ line and clocked into the 8-bit 
shift register on the low-to-high transition of CLK. The ST 
line must be set low during the low time of CLK. Data is ac- 
cepted on low-to-high transition of the clock while the high- 
to-low transition of CLK increments the bit counter. After 8 
data bits have been entered the final high-to-low transition 
of CLK sets an internal latch tied to the BDONE line (Pin 
15). At the same time, the contents of the shift register are 
parallel loaded into an 8 bit register making the parallel data 
available on the D00-D 07 o utputs. BDONE will remain in a 
latched state until the BCLR is set to a logic 0, clearing off 
the BDONE signal. BCLR is a level triggered input and 
must be set back to a logic 1 before the next 8 bits are 
shifted through the register, BCLR has no effect on the 
serial shifting process. When the next 8 bits are received, 
BDONE will again be set and the operation continues. 



When interfacing to a microprocessor, BDONE is used to 
indicate a parallel byte is ready to be read. As the processor 
reads the data out of the D00-D07 lines, the BCLR line 
should be strobed to clear off BDONE in anticipation of the 
next assembled byte. An address decode signal generated 
at the host may be used for this purpose. During a power- 
up condition, the state of BDONE is indeterminant. It is 
recommended that BCLR be strobed low after power-up to 
insure that BDONE is cleared. 

The serial output line from the last stage of the shift 
register is available on t he DOUT pin. An inverted copy of 
CLK is availab le on the SHFCLK pin. Both DOUT (Pin 16) 
and SHFCLK (Pin 14) can be used to drive another shift 
register external to the device. 



The three signals BDONE, DOUT, and SHFCLK can be 
placed in a high impedance state by setting EN (Pin 
19) to a logic 0. Likewise, EN must be at a logic 1 in 
order for these signals to be active. 

The TEST pin is internally OR'ed with th e ST l ine to inhibit 
the bit counter. It is recommended that TEST be left open 
by the user. An internal pull-up resistor is tied to this pin to 
satisfy the appropriate logic level required internally for 
proper device operation. 



36 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°C to 50°C 

Voltage on any pin 

with respect to Vss - 0.2V to + 7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTIC - 55 °C to + 125 g C 

CERAMIC - 55 °C to + 150°C 



NOTE: Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tions at these limits is not intended and should be 
limited to those conditions specified in the DC 
electrical characteristics. 






o 
o 



DC Electrical Characteristics Ta = 0°Cto50°C; Vcc = +5V ± 10%,Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vo 


Output Low Voltage 






0.4 


V 


lOL = 3-2 mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = - 200 M A 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 






100 


mA 


All Outputs Open 



AC Electrical Characteristics Ta = 0°to50°C,Vcc = 5V±10%,Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNITS 


CONDITION 


fCL 


CLK FREQUENCY 







5.25 


MHZ 




tLS 


4 CLK to ST 









nsec 


ST = 1 (min 200nsec) 


tHS 


t CLK to ST 









nsec 


ST = 1 (min 200nsec) 


tDS 


Data set-up tot CLK 


15 






nsec 




WB 
tRS 
*BW 

tsc 
tcs 

tSD 


BDONE valid from t CLK 


65 
50 




110 
110 

90 

100 

55 


nsec 
nsec 
nsec 
nsec 
nsec 
nsec 


m m m m m m 
z z z z z z 

II II II II II II 


BDONE reset from BCLR 


BCLR Pulse Width 


tCLKtolSHFCLK 


ICLKtofSHFCLK 


Data delay from t SHFCLK 


tFO 


Enable to DOUT ACTIVE 






90 


nsec 




tDH 


Data Hold w.r.t. t CLK 


25 






nsec 





NOTES: 1. Typical Values are for Ta = 25°CandVcc = +5.0V 



37 



o 

8 



CLK 
ST 



jnj^jrj^JOJ^JiJ^j"i^ajij _ LJTjru^jT_nj" 



LS I I i 'MS 
— »-i i ,-* - 



-byle 1 or n- 



nrz :;;;xzxiXD(7XD(Z)G^QXDGXixrx 

i I 

j X i X b y |e 1 or n 



DOX X X Powor-On DATA / byte n-1 

BDONE 



BCLR 




tcs . 



I . *sc 



IT 



njnJ~l_ruTJi_rLn 



SHFCLK^ 

EN I 



WD1 100-01 
Figure 3. 



See page 725 for ordering information. 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



38 



Western Digital 

WD1 100-02 MFM Generator 



DESCRIPTION 

The WD1 100-02 MFM Generator converts NRZ data into an 
MFM (Modified Frequency Modulated) data stream. The 
derived MFM signal containing both clocks and data can 
then be used to record information on a Winchester Disk 
Drive utilizing this recording technique. In addition to an 
MFM output, the device generates first level Write 
Precompensation signals for use with inner track densities, 
A unique feature of the WD1 100-02 is the ability to delete a 
clock pulse in the outgoing MFM stream in order to record 
Address Marks. 



o 

s 



The WD1 100-02 is fabricated in NMOS silicon gate 
technology and is available in a 20 pin plastic or ceramic 
dual-in-line package. 

FEATURES 

• SINGLE +5V SUPPLY 

• 5 MBIT/SEC DATA RATE 

• WRITE PRECOMPENSATION 

• ADDRESS MARK GENERATION 

• 20 PIN DIP PACKAGE 





RWC 



NRZ *_ 



WCLK >. 



WCLK ^- 



4 BIT 

SHIFT 

REG. 



WRITE 

PRECOMP 

GEN. 



MFM GEN 



SKPEN ,_ 



+. EARLY 
■+- NOM 
-»► LATE 



-*- MFM 



"SKIP" 
LOGIC 



WD1 100-02 
Figure 2. Block Diagram MFM Generator 



DRQCLK >- 
INTCLK »~ 



D 



Q 0- 



A0 >. 




DECODE 

LOGIC 



■op CP 

s 

IT 



DfiQ 



D Q 
Ob CP 



■♦-INTRQ 



WD1 100-02 
Figure 1. Pin Connections 



WD1 100-02 
Figure 3. Block Diagram Interrupt Control Logic 



39 



PIN 
NUMBER 



1 



4 
5 

9 

10 

11 

12 

13 

16 

6 
8 

7 

15 

14 

17 
18,19 

20 



SYMBOL 



NRZ 
SKPEN 

WCLK 

WCLK 
RWC 

NC 

vss 

NOM 

LATE 

EARLY 

MFM 

CS 
INTCLK 

DRQCLK 



NAME 



INTRQ 



DRQ 



MR 



Ao.Ai 



vcc 



NON-R ETURN-TO 
ZERO 

SKIP ENABLE 

WRITE CLOCK 

WRITE CLOCK 

REDUCED WRITE 
CURRENT 

No Connection 

VSS 
NOMINAL 

LATE 

EARLY 

MFM DATA 

CHIP SELECT 



FUNCTION 



INTERRUPT 

REQUEST CLOCK 

DATA R EQUEST 
CLOCK 



INTERRUP T 
REQUEST 



DATA REQUEST 



MASTER RESET 



ADDRESS 1,0 



VCC 



NRZ data input that is strobed into the MFM generator by 
WCLK(i). 

This input arms the SKIP logic for recording Address Marks 
when set to a logic 1 . 

Complimentary clock inputs. NRZ data is clocked into the 
MFM Generator on the high-to-low transition of 
WCLK (pin 3). 

This signal when high, enables EARLY, LATE and NOM 
outputs. 

No Connection. 

Ground. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be written nominal. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be shifted LATE before writing. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be shifted EARLY before writing. 

This output contains the MFM encoded data derived from 
the NRZ (pin 1) line. 

Low input signal used to enable the Address decode logic. 

A high-to-low transition on this line will latch the 
INTRQ (pin 15) at a logic 0. 

A high-to-low transition on this line will latch the DRQ (pin 
14) at a logic 0. 

This output is latched at a logic when INTCLK (pin 8) 
makes a high-to-low transition while the decode logic is 
disabled. 

This output is latched at a logic when DRQCLK (pin 7) 
makes a high-to-low transition while the decode logic is 
disabled. 

A low level on this line causes DRQ and INTRQ to set at a 
logic 1. 

When CS is low and the address lines are high, INTRQ is 
cleared; if the address lines are low then DRQ gets cleared, 
(i.e. set at a logic 1). 

+5V ±10% power supply input. 



DEVICE DESCRIPTION 

The WD1 100-02 is divided into two sections: MFM 
Generator and Interrupt Logic. The MFM Generator con- 
verts NRZ data into MFM data and provides Write 
Precompensation signals. The Interrupt Logic is used 
specifically on the WD1000 Winchester Controller Board 
and may be used in similar designs to generate Interrupt 
signals. The two sections of the device are isolated and 
have no common input or output signals. 



Prior to entering data, the SKPEN line must be set to a logic 
to en able only clocks in the data stream. Data is entered 
on the NRZ line and strobed on the high-to-low transition of 
WCLK. The encoded NRZ data appears on the MFM (pin 16) 
output lagging by one clock cycle. 

Write Precompensation signals EARLY, LATE, and NOM are 
generated as each data or clock pulse becomes available at 
the input when RWC is logic 1. The algorithm used is on 
Page 8. 



40 





LAST DATA SENT 


SENDING 


TO BE SENT 
NEXT 


EARLY 


LATE 


NOM 


X 1 


1 





H 


L 


L 


X 


1 


1 


L 


H 


L 








1 


H 


L 


L 


1 








L 


H 


L 


ANY OTHER PATTERN 






L 


L 




H 





3 



DEVICE DESCRIPTION (CONTINUED) 

The SKPEN signal is used to record a unique data/clock 
pattern as an Address Mark, using Al-je data with OA^ 
clock. This pattern is used for synchronization prior to data 
or ID fields that are read from the disk. 
When the SKPEN signal is set to a logic 1, the internal skip 
logi c is e nabled. As long as zeroes are being shifted into 
the NRZ line, the device generates normal MFM data. On 
receipt of the first non-zero bit (typically the MSB of the 
A1 16 the skip logic begins to count WCLK cycles. When the 
MFM generator tries to produce a clock between data bits 2 
and 3, the skip logic disables the MFM generator during 
that time. The result for A1 16 data is a clock pattern of 0A 16 
instead of OE 16 . Although other data patterns may be used, 
the MSB of the pattern must be a 1 (80 16 or higher) in order 
to enable the skip logic at the proper time. After the skip 
logic has performed, it then disables itself and MFM data 
is recorded normally starting with the succeeding byte. 
To re-enable the skip logic again, the SKPEN line must be 
strobed. 



The Interrupt Logic is u sed to c lear Data Requests (DRQ) 
and Interrupt Requests (INTRQ) by selecting CS (pin 6) in 
combination with Ap and Ay The M R (Master Reset) signal 
is used to clear both DRQ and INRQ simultaneously. 



MR 


*i 


Ao 


CS 


DRQ 


INTRQ 





X 


X 


X 


H 


H 




X 


X 


1 


Qn 


Qn 













H 


Qn 




1 


1 





Qn 


H 




1 








Qn 


Qn 







1 





Qn 


Qn 



X = Don't care 

Q N = remains at previous state 



DRQ and INTRQ can be set to a logic o nly on the high-to- 
low transition of DRQCLK and INTCLK respectively. The 
signal will remain at a logjcO until cleared by a MR or pro- 
per address selection via CS, At, and Aq. 



41 



o 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°c to 50°c 

Voltage on any pin with respect to Vss • ■ - 0-2V to + 7.0V 
Power Dissipation 1 Watt 

STORAGE TEMPERATURE: 

PLASTIC -55°Cto +125°C 

CERAMIC -55°Cto +150°C 



NOTE: Maximum ratings indicate operation when perma- 
nent device damage may occur. Continuous opera- 
tion at these limits is not intended and should be 
limited to those conditions specified in the DC Elec- 
trical Characteristics. 



DC Electrical Characteristics Ta = 0°Cto50°C, V<x = +5V ± 10%, Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


VlL 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


lOL = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = - 200^A 


voc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




<cc 


Supply Current 






100 


mA 


All outputs open 



AC Electrical Characteristics Ta = 0°Cto50°C; Vqc = +5V 


± 10%; Vss = 0V 






SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


fwc 


WCLK FREQUENCY 






5.25 


MHZ 




*DS 


Data Setup w.r.t A WCLK 


10 






nsec 




tDH 


Data hold w.r.t. 1 WCLK 


25 






nsec 




tMF 


t WCLK to tMFM delay 






160 


nsec 


Pin 1 LOW 


tFM 


i WCLK to4MFM delay 






180 


nsec 


Pin 1 LOW 


tWN 


Data delay to NOM from 
mCLK 






190 


nsec 


Pin 4 = LOW 


tWE 


Data delay to EARLY from 
I WCLK 






180 


nsec 


Pin 4 = LOW 


tWL 


Data delay to LATE from 
iWCLK 






180 


nsec 


Pin 4 = LOW 


*MR 


Master reset pulse width 


50 






nsec 




*MD 


i MR to t DRQ 







150 


nsec 





42 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


tMI 

tDQ 

t|Q 

tDD 

til 

tAD 

tAI 

tCD 

tci 

tRN 


^MRtotlNTRQ 


50 
50 




150 

120 
120 
145 
160 
145 
180 
115 


nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 
nsec 




DRQCLK pulse width 


INTCLK pulse width 


i DRQCLK to DRQ 


* INTCLK to INTRQ 
i AX tot DRQ 


fAXtotlNTRQ 
i CS to t DRQ 


ICStotlNTRQ 
tRWCtoiNOM 



o 



NOTES: 1. Typical Values are for Ta = 25°CandVcc = +5.0V. 



WCLK 




WD1 10002 
Figure 4. MFM Generator Timing 



-^ l MR|- 



-*-; .— '■up 

DRQ ! 



intrq' \ 



— x m 



WD1 100-02 
Figure 5 



—J'dqJ— 



DRQCLK 



DRQ 



-^rpM, 



DO 



WD1 10002 
Figure 7. 



CSorAX — I 



'CD or 'AD | 
DR Q_j_,^ t| 

INTRQ 



CI 



WD1 10002 
Figure 6 




INTCLK 



INTRQ 



WD1 100-02 
Figure 8. 



See page 725 for ordering information. 



43 



o 



o 
o 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



. . Printed in U 5 A 

44 



Western Digital 

WD1 100-12 Improved MFM Generator 



DESCRIPTION 

The WD1 100-12 improved MFM Generator converts NRZ 
data into an MFM (Modified Frequency Modulated) data 
stream. The derived MFM signal containing both clocks 
and data can then be used to record information on a 
Winchester Disk Drive utilizing this recording technique. In 
addition to an MFM output, the device generates first level 
Write Precompensation signals for use with inner track 
densities. A unique feature of the WD1 100-12 is the ability 
to delete a clock pulse in the outgoing MFM stream in 
order to record Address Marks. 



The WD1 100-12 is fabricated in NMOS silicon gate 
technology and is available in a 20 pin plastic or ceramic 
dual-in-line package. 



FEATURES 

• SINGLE + 5V SUPPLY 

• 5 M BIT/SEC DATA RATE 

• WRITE PRECOMPENSATION 

• ADDRESS MARK GENERATION 






O 

o 



NRzd 1 
SKPEN^ 2 

wclkLZ 




JINTRQ 

ZDdrq 

]EARLY 

lLATE 

|NOM 



RWC J*- 



NRZ 



WCLK»- 



WCLKi 



4 BIT 

SHIFT 

REG. 



2XDR 



"1 



WRITE 

PRECOMP 

GEN. 



MFM GEN 



SKPEN 



EARLY 

NOM 

LATE 



MFM 



"SKIP" 
LOGIC 



WD1100-12 
'Figure 2. Block Diagram MFM Generator 



DRQCLK >- 



INTCLK*- 



A0: 



A1 *- 



CS»- 



DECODE 
LOGIC 



D s o:> 



rOpCP 

R 



T 



DRQ 



D Q-p- 

rOt>CP 

R 



MR»- 



INTRQ 



WD1100-12 
Figure 1. Pin Connections 



WD1100-12 
Figure 3. Block Diagram Interrupt Control Logic 



45 



PIN 
NUMBER 



1 



10 
11 

12 

13 

16 

6 
8 

7 

15 

14 

17 

18,19 

20 



SYMBOL 



NRZ 
SKPEN 

WCLK 

WCLK 
RWC 



2XDR 

vss 

NOM 

LATE 

EARLY 

MFM 

CS 
INTCLK 

DRQCLK 



NAME 



INTRQ 



DRQ 

MR 

Ao,Ai 

vcc 



NON-RETURN-TO 
ZERO" 

SKIP ENABLE 



WRITE CLOCK 

WRITE CLOCK 

REDUCED- WRITE 
CURRENT 



2 TIMES 
DATA RATE 

VSS 
NOMINAL 

LATE 

EARLY 

MFM DATA 

CHIP SELECT 

INTERRUPT 

REQUEST CLOCK 

DATA R EQUEST 
CLOCK 



FUNCTION 



INTERRUP T 
REQUEST 

DATA REQUEST 



MASTER RESET 



ADDRESS 0,1 



vcc 



NRZ data input that is strobed into the MFM generator by 
WCLK(I). 

This input arms the SKIP logic for recording Address Marks 
when set to a logic 1. 

Complimentary clock inputs. NRZ data is clocked into the 
MFM Generator on the high-to-low transition of WCLK 
(pin 3). 

This signal when high, enables EARLY, LATE and NOM 
outputs. 

This input is used to latch EARLY, LATE, NOM and MFM 
outputs. 

Ground. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be written nominal. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be shifted LATE before writing. 

Output signal from the Write Precompensation Logic used 
to signify that data is to be shifted EARLY before writing. 

This output contains the MFM encoded data derived from 
the NRZ (pin 1) line. 

Low input signal used to enable the Address decode logic. 

A low on this line will latch the INTRQ (pin 15) at a logic 0. 

A low on this line will latch the DRQ (pin 14) at a logic 0. 

This output is latched at a logic when INTCLK (pin 8) 
goes/ is low. 

This output is latched at a logic when DRQCLK (pin 7) 
goes/is low. 

A low level on this line causes DRQ and INTRQ to set at a 
logic 1. 

When CS is low and the address lines go high, INTRQ is 
cleared; if the address lines go low then DRQ gets cleared, 
(i.e. set at a logic 1). 

+ 5V + 10% power supply input. 



DEVICE DESCRIPTION 

The WD1 100-12 is divided into two sections: MFM 
Generator and Interrupt Logic. The MFM Generator con- 
verts NRZ data into MFM data and provides Write 
Precompensation signals. The Interrupt Logic is used 
specifically on the WD1000 Winchester Controller Board 
and may be used in similar designs to generate Interrupt 
signals. The two sections of the device are isolated and 
have no common input or output signals. 



Prior to entering data, the SKPEN line must be set to a logic 
to en able only clocks in the data stream. Data is entered 
on the NRZ line and strobed on the high-to-low transition of 
WCLK. The encoded NRZ data appears on the MFM (pin 16) 
output lagging by one clock cycle. 

Write Precompensation signals EARLY, LATE, and NOM 
are generated as each data or clock pulse becomes 
available at the input when RWC is logic 1. The algorithm 
used is on Page 4. 



46 



LAST DATA SENT 


SENDING 


TO BE SENT 
NEXT 


EARLY 


LATE 


NOM 


X 1 


1 





H 


L 


L 


X 


1 


1 


L 


H 


L 








1 


H 


L 


L 


1 








L 


H 


L 


ANY OTHER PATTERN 






L 


L 


H 



DEVICE DESCRIPTION (CONTINUED) 

The SKPEN signal is used to record a unique data/clock 
pattern as an Address Mark, using A1 16 data with 0A 16 
clock. This pattern is used for synchronization prior to data 
or ID fields that are read from the disk. 

When the SKPEN signal is set to a logic 1, the internal skip 
logic is enabled. As long as zeroes are being shifted into 
the NRZ line, the device generates normal MFM data. On 
receipt of the first non-zero bit (typically the MSB of the 
A1 16 the skip iogic begins to count WCLK cycles. When the 
MFM generator tries to produce a clock between data bits 2 
and 3, the skip logic disables the MFM generator during 
that time. The result for A1 16 data is a clock pattern of 0A 16 
instead of OE 16 . Although other data patterns may be used, 
the MSB of the pattern must be a 1 (80 16 or higher) in order 
to enable the skip logic at the proper time. After the skip 
logic has performed, it then disables itself and MFM data 
is recorded normally starting with the succeeding byte. 
To re-enable the skip logic again, the SKPEN line must be 
strobed. 

The Interrupt Logic is u sed to clear Data Requests (DRQ) 
and Interrupt Requests (INTRQ) by selecting CS (pin 6) in 
combination with Ap and A-t. The M R (Master Reset) signal 
is used to clear both DRQ and INRQ simultaneously. 



MR 


Ai 


Ao 


CS 


DRQ 


INTRQ 





X 


X 


X 


H 


H 




X 


X 


1 


Q N 


Q N 













H 


Qn 




1 


1 





On 


H 




1 








Qn 


Qn 







1 





On 


Qn 



X = Don't care 

Q N = remains at previous state 



3 



DR Q and INT RQ c an be set to a logic only by a low level 
or DRQCLK and INTCLK respectively. The signal will 
remain at a logic until cleared by a MR or proper address 
selection viaCS, A 1( and Aq. 



47 



D 



o 

o 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0"Cto50°C 

Voltage on any pin with respect to Vss ■ ■ • - 0.2V to + 7.0V 
Power Dissipation 1 Watt 

STORAGE TEMPERATURE: 

PLASTIC - 55°C to + 125°C 

CERAMIC - 55°C to + 150X 



NOTE: Maximum ratings indicate operation when per- 
manent device damage may occur. Continuous 
operation at these limits is not intended and should 
be limited to those conditions specified in the DC 
Electrical Characteristics. 



DC Electrical Characteristics T A = 0°Cto50°C; Vcc = +5V ± 10%; Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


Iql = 3-2 mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = - 200 M A 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 






100 


mA 


All outputs open 



AC Electrical Characteristics Ta = 0°Cto50°C; Vcc = +5V ± 10%; Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


tFR 


WCLK FREQUENCY 






5.25 


MHZ 




tDS 


Data Setup w.r.t. 4 WCLK 


10 






nsec 




tDH 


Data hold w.r.U WCLK 


25 






nsec 




tMF 


t WCLK to tMFM delay 






210 


nsec 


Pin 1 LOW 


tFM 


1 WCLK to i MFM delay 






230 


nsec 


Pin 1 LOW 


tWN 


Data delay to NOM from 
iWCLK 






240 


nsec 




*WE 


Data delay to EARLY from 
IWCLK 






230 


nsec 




tWL 


Data delay to LATE from 
4 WCLK 






230 


nsec 




tMR 


Master reset pulse width 


50 






nsec 




tMD 


iMRtotDRQ 






150 


nsec 





48 













SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 




*MI 
tDQ 
t|Q 
*DD 

til 


I MR tot INTRO. 


50 
50 




150 

120 
120 


nsec 
nsec 
nsec 
nsec 
nsec 




DRQCLK pulse width 




INTCLK pulse width 


i 


i DRQCLK to DRQ 




4 INTCLK to INTRO 




*AD 
tAI 


i AX tot DRQ 






145 
160 


nsec 
nsec 






tAXtotlNTRQ 




tCD 

tci 


4 CS tot DRQ 






145 
180 


nsec 
nsec 






iCStotlNTRQ 




tRN 


t RWC to I NOM 






145 


nsec 






tTE 


4 2XDR tot EARLY 






75 


nsec 






*TN 


4 2XDRtotNOM 






75 


nsec 






.TL 


42XDR tot LATE 






75 


nsec 







NOTES: 1. Typical Values are for T A = 25°CandVcc = +5.0V 



WCLK 
NR2 

MFM 



-TTJTirLJ^LrLrTJ^JTJT^^ 



i i 



tMF!-~, 



{| »FM 



I 



n — oo- 



A116- 



-J^IJ^IJTJ^^ 



2XDR 

EARLY 
NOM 

LATE 
RWC 



!_r^i i : i 5 i ; 



| "Sf-tTN 



i_r 



<WN — *•! •*— 



!•*— *WL 

J^L_ 



LJ-nj - " 

—if— tTL 

R_ 



tRN- 



WD1 100-12 Figure 4 MFM GENERATOR TIMING 



49 



o 
8 



■HtMR!* 




> H*- l M I 

i ntrq_j 

WD1100-12 Figure 5 



— H 1 dqK- 




WD1100-12 Figure 7 



CS or AX 
tCD ort AD i 




INTRQ 

WD110012 Figure 6 



•— I 'iq t— 

INTCLK I I 



INTRQ 



WD1100-12 Figure 8 



See page 725 for ordering information. 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



50 



Printed in (J S .A 



Western Digital 

WD1 100-03 AM Detector 



DESCRIPTION 

The WD1 100-03 Address Mark Detector provides an effi- 
cient means of detecting Address Mark Fields in an MFM 
(NRZ) data stream. MFM (NRZ) clocks and data are fed to 
the device along with a window clock generated by an ex- 
ternal data separator. The WD1 100-03 searches the data 
stream for a DATA = A1, CLK = 0A pattern and produces 
an AM DET signal when the pattern has been found. NRZ 
data is an output from the device, which can be used to 
drive a serial/parallel converter. An uncommitted latch is 
also provided for by the data separator circuitry, if required. 






The WD1 100-03 Address Mark Detector is fabricated in 
NMOS silicon gate technology and is available in a 20 pin 
dual-in-line package. 

FEATURES 

• SINGLE + 5V SUPPLY 

• 5 MBITS/SEC DATA RATE 

• DECODES A1 16 -0A 16 

• SYNCHRONOUS CLOCK/DATA OUTPUTS 

• 20 PIN DIP PACKAGE 















































+5V- 




D 
> Q 

R 






RST >- 






*" QOUT 


"qJN >— ■ 






t 








1 
2 
3 
4 
5 
6 
7 
8 

g 

10 


20 
9 
8 

6 
5 
4 
3 
2 


H v cc 

I RST 

Z3 cp 

I NC 

I AMDET 






RCLK | 

57n rj^ 

RCLK Q 
CLK IN (Z 












D 

C 
R 


Q 

8 BIT 
SHIFT REG 






fVM IT 




Q 










DOUT | 

NC f^ 

nc r_m 

TEST 1 d 
ENDET £Z 

v ss C 




'' 




























I AMDET 

I qoDt 

I NC 
I DCLK 
I TEST 2 






r~ 






R DETECT A1 
DETECT 0A 












^ 1* AMDET 




6 
















I 




















R 
D 

C 


Q 

8 BIT 
SHIFT REG 








CLK IN > 



























WD1 100-03 
Figure 1. Pin Connections 



WD1100-03 
Figure 2. Block Diagram 



51 



a 



© 
o 



PIN 
NUMBER 



6,7,13,17 

8 
11 



10 
12 
14 
15 

16 
18 
19 
20 



SYMBOL 



RCLK 
RCLK 

DIN" 



CLKIN 



DOUT 



NC 



TEST1 
TEST 2 

ENDET 

vss 

DCLK 



QOUT 
AMDET 

AMDET 

CP 

RST 

vcc 



NAME 



READ CLOCK 
READ CLOCK 

DATA INPUT 



CLOCK INPUT 



DATA OUTPUT 



No Connection 



TEST 1 
TEST 2 

ENABLE 
DETECTION 

vss 

DATA CLOCK 

LATCH OUTPUT 

ADDRES S MARK 
DETECT 

ADDRESS MARK 
DETECT 

CLOCK PULSE 



RESET 



VCC 



FUNCTION 



Complimentary clock inputs used to clock DIN and CLK IN 
into the AM detector. 

MFM data pulses from the external Data Separator are con- 
nected on this line. 

MFM clock pulses from the external Data Separator are 
connected on this line. 

Data Output from the internal Data Shift register, syn- 
chronized with DCLK. 

To be left open by the user 

To be left open by the user. 

A logic 1 on this line enables the detection logic to search 
for a data A1 ^ and clock. 

GROUND. 



Clock output that is synchronized with DATA OUT (Pin 5). 

Signal output from the uncommitted latch. 

Complimentary Address Mark Detector output. These 
signals will go active when a Data = A1 16 Clock = 0A 16 
pattern is detected in the data stream. 



A low-to-high transition on this line will cause the QOUT 
(Pin 14) to be latched at a logic 0. 

A logic on this line will cause the QOUT (Pin 14) signal to 
be set at a logic 1. 

+ 5V ± 10% power supply input. 



DEVICE DESCRIPTION 

Prior to shifting data through the device, the internal logic 
must be initialized. While the ENDET (Pin 9) line is_at a logic 
0, shifting of data will be inhibited and AMDET, AMDET, 
CLK, and DATA OUT will remain inactive. 

When ENDET is Erta logic 1, shifting is enabled. NRZ data is 
entered on the D IN line (Pin 2) and shifted on the high-to- 
low transition of RCLK (Pin 1). NRZ clocks are entered on 
the CLK IN line, a nd shif ted on the high-to-low transition of 
RCLK (Pin 3). The DOUT line (Pin 5) is tied to the last stage 
of the internal Data Shift register and will reflect informa- 
tion clocked into the DIN line delayed by 8 bits. 
While each bit is being shifted, a 16 bit comparator is con- 
tinuously checking the parallel contents of the shift 
registers for the DATA = A1 16 , CLK = 0A 16 pattern. When 
this pattern is detected, AMDET w[IJ_be set to a logic and 
AMDET will be set to a logic 1. AMDET and AMDET will re- 
main latched until the device is re-initialized by forcing 
ENDET to a logic 0. 



When an AM i s detec ted, DCLK will begin to toggle. Data 
present on the DOUT line may then be clocked into an ex- 
ternal serial/parallel converter. DCLK will remain inactive 
when ENDET is held at a logic 0. 

An uncommitted edge-triggered flip/flop has been provided 
to facilitate the detection of high frequency by the data 
separator, but may be used for any pu rpose. The low-to- 
high tra nsition of CP (Pin 18) will set the QOUT (Pin 14) to a 
logic . QO UT may be reset back to a logic 1 by a low level 
on the RST line (Pin 19). 

TEST1 and TEST2 are output lines. TE ST1 is an active low 
pulse when an A1 16 is detected, and TEST2 is active low 
pulse when a 0A 16 is detected. These signals are 
used for test points and therefore should be left open by 
the user if not required. 



52 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under bias 0°Cto50°C 

Voltage on any pin with respect to Vss ■ • ■ - 0.2V to + 7.0V 
Power dissipation 1 Watt 



STORAGE TEMPERATURE 

PLASTIC - 55°C to + 125°C 

CERAMIC - 55°C to + 150°C 

NOTE: Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tions at these limits is not intended and should be 
limited to those conditions specified in the DC elec- 
trical characteristics. 



3 



o 
o 



DC Electrical Characteristics Ta = 0°Cto50°C 


V C C= +5V 


± 10%, V S c 


j =-- OV 






SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 




-0.2 




0.7 


V 




V|H 


Input High Voltage 




2.0 






V 




vol 


Output Low Voltage 








0.4 


V 


lOL = 3.2 mA 


voh 


Output High Voltage 




2.4 






V 


lOH = - 200 M A 


vcc 


Supply Voltage 




4.5 


5.0 


5.5 


V 




ice 


Supply Current 








100 


mA 


All outputs open 



AC Electrical Characteristics Ta = 0°Cto50°C; Vcc = +5V ± 10%, Vss = 0V 



SYMBOL 


PARAMETER 


fRC 


RCLK Frequency 


tST 


Data Setup time 


*HT 
*DD 
tRD 
tRA 
tRM 
tRO 


Data Hold time 


DOUT to DCLK DELAY 


IRCLKtotDCLK 


iRCLKtotAMDET 


IRCLKtolAMDET 


1 RCLK to DOUT 


tEA 
tRQ 


lENDETtolAMDET 


1 RST to t QOUT 


tRW 


Pulse width of RST 


tew 

tCQ 


CP Pulse width 


tCPtolQOUT 



MIN 



40 
10 



TYP 1 



50 
90 



MAX 



UNIT 



5.25 


MHZ 




nsec 




nsec 


110 


nsec 


120 


nsec 


115 


nsec 


125 


nsec 


135 


nsec 


130 


nsec 


110 


nsec 




nsec 




nsec 


106 


nsec 



CONDITION 



NOTES: 1. Typical Values are for Ta = 25°CandVcc = + 5V - 



53 



3 

o 



o 

o 



ENDET 



RCLK 
DIN 

RCLK 

cTkTn 

TEST"! 
TEST"! 

AMDET 

AMDET 
DOUT 

DCLK 




T_n_n_rLn_ 

■si^i u. i 'ht 

I»|1 i»0 10 



1 fpc I 



i_r~L 



"LTLTL 




"LrLTLTLTLr 
-•- t RD 



J~LJUl^lJ"!li~"LJT_l 



i*- 



-OA- 



(STDFT) 



(OADET) 



! t„ 



: t B 



start of A1 





_r 



i_ 



rLTLTLTI 



WD1 10003 
Figure 3. Functional Timing 



See page 725 for ordering information. 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



54 



Printed in U S A 



Western Digital 

WD110004 CRC Generator/Checker 



DESCRIPTION 

The WD1 100-04 CRC Generator/Checker is designed to 
generate a Cyclic Redundancy Checkword from a serial 
data stream, and to check a data stream against a known 
CRC word. Complimentary latched "CRCOK" outputs are 
provided to indicate CRC errors in check mode. Additional 
logic has been included to shift the CRC checkword out of 
the device by signals generated on other WD1100 family 
devices. 

The WD1 100-04 is fabricated in NMOS silicon gate 
technology and is available in a 20 pin dual-in-line package. 






O 

o 



FEATURES 

• GENERATES/CHECKS CRC 

• SINGLE +5V SUPPLY 

• LATCHED ERROR OUTPUTS 

. X16 + X12 + X5 + 1 (CCITT-16) 

• AUTOMATIC PRESET 

• 20 PIN DIP PACKAGE 



5Tn 


z 
z 
z 


1 


DOCK 


2 


SHFCLK 


3 


NC 


Z 


4 


NC 


Z 


5 


CWE 


IZ 


6 


DOCE 


z 
z 




CRCIZ 


8 


NC 


z 


9 


vss 


c 


10 



-v_y~ 



Zl v cc 

I NC 
I NC 
| NC 
I CRCOK 
I TIMCLK 
I WCLK 
I CRCOK 
I SKPCLK 
I DOUT 



CRCIZ >- 



DIN 



SHFCLK >- 



D S 



OC 



-SKPCLK 



POLYNOMIAL GEN 



x 16 +x12 



X 5 + 1 



DOCE 



DOCK >- 



WD1 100-04 
Figure 1. Pin Connections 



D 



-oC 




DOUT 



-*- CWE 



H>°- 



CRCOK 
CRCOK 



WCLK 



4- 16 



-*► TIMCLK 



WD1 100-04 
Figure 2. Block Diagram 



55 






o 
o 



PIN 
NUMBER 



1 



4,5 
6 



g 

10 

11 

12 
13 

14 

15 

16 

17-19 
20 



SYMBOL 



DIN 



DOCK 



SHFCLK 



N.C. 
OWE 



DOCE 



CRCIZ 



N.C. 

vss 

DOUT 



SKPCLK 



CRCOK 



WCLK 



TIMCLK 
CRCOK 

N.C. 
VCC 



NAME 



DATA INPUT 



DATAORCR C 
WORD CLOCK 



SHIFT CLOCK 



NO CONNECTION 

CHECK W ORD 
ENABLE 

DATA OR CRC 
ENABLE 



CYCLIC 



REDUNDANCY 
CHECK INITIALIZE 

NO CONNECTION 

GROUND 

DATA OUTPUT 



SKIP CLOCK 



CYCLIC 
REDUNDANCY 
CHECK OKAY 

WRITE CLOCK 



TIMING CLOCK 



CYCLIC 



REDUNDANC Y 
CHECK OKAY 

NO CONNECTION 
VCC 



FUNCTION 



Active low serial input data stream is used to 
generate/check the 2 byte CRC word. 

After a byte of data has been transferred in, this input 
signal is used to latch the state of DOCE in an internal 
D flop with a high to low transition. 

The falling edge shifts data bits into the CRC 
genera tor/checker. It also transfers the CRC check word to 
DOUT in the write mode (DOCE = LOW). The rising edge 
also activates the CRCOK lines in the read mode when no 
error is found. 



This active low outp ut indi cates that th e CRC checkword is 
being output on the DO UT line. When CWE is high, data is 
being output on DOUT. 

Initially, this input line is held high to direct input data (pin 
1) to the output data (pin 1 1). After the next to the last BYTE 
is transmitted but before the last BYTE occurs DOCE must 
be low to direct the 2 CRC check bytes to DOUT (pin 11). 

DOCE must be maintained low for a minimum of 2 byte 
times. DOCE is used only in the write mode. 

When this line is at a logic 0, the SKPCLK output line is 
held high and the CRC generator is held preset to hex 
"FFFF." 



GROUND. 

In the write mode, this line outputs the unmodified data 
stream along with the 2 byte CRC word appended to the 
end of the stream. 

The first high-to-low transition on DIN (pin 1) resets 
SKPCLK low and enables the CRC to either generate or 
check the CRC word. 

In the read mode, after the 2 byte CRC word is entered 
on DIN and no error has been detected, this line is set 
high to indicate no errors hav e occurred. This line will 
then remain high as long as DIN is maintained high. 

This input clock is divided by 16 to produce TIMCLK 
(pin 15) and has no effect on the rest of the internal cir- 
cuitry. 

See above. 

Complementary output version of CRCOK (pin 13). 



+ 5V ± 10% power supply input. 



56 



DEVICE DESCRIPTION 

Prior to shifting data thru the device (either in the read or 
write modes) the C RC generator/checker is initialized by 
strobing the CRCIZ (pin 8) low. This forces the SKPCLK (pin 
12) line to the high state. The first low going transition on 
DIN (pin 1), namely the most significant bit of an address 
mark, resets the SKPCLK line. The WD1 100-04 has now 
been properly initialized and is r eady to generate/check the 
CRC bytes. The CRCOK and CRCOK lines should be set to 
their inactive states. 

In the writ e mode , initially the DOCE (pin 7) is held high and 
a pseudo DOCK is produced by supplying a string of zeros 
before the address mark. This ensures the proper state of 
the internal D flip flop to gate input data to the output line 
DOUT (pin 1 1). As shown in the block diagram the CWE (pin 
6) will be set high. Sometime between the next to the last 
and the last DOCK that indicates the end of the data 
stream, DOCE (pin 7) is lowered to ensure the smooth tran- 
sition of the 2 byte CRC checkword to the output line 
DOUT (pin 11). 

DOCE must be maintained low for a minimu m of 2 byte 
times. After the CRC word is generated, DOUT will produce 
a string of zeros (i.e., held high). This portion of the circuitry 
is dormant in the read mode. 

After proper initialization, input data is entered on DIN (pin 
1) along with the 2 byte CRC word for the read mode of 

DC Electrical Characteristics Ta = 0°C to 50°C; Vcc = +5V ± 



operation. At the end of the data stream, if no errors were 
detected the CRCOK (pin 13) is set high. Accordingly the 
complimentary output (pin 16) is s et low . These output 
states will be maintained as long as DIN is held high and 
CRCIZ (pin 8) is not strobed. If the CRCOK lines do not 
become active, an error has been detected and a re-try is in 
order. If successive re-tries fail, an error flag may be set to 
determine a further course of action as desired by the user. 

WCLK is divided by 16 to produce TIMCLK which may be 
used as a buffered step clock for SA1000 compatible 
drives. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°c to 50°c 

Voltage on any pin with respect to Vss . . . - 0.2V to + 7.0V 
Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTIC - 55 °C to + 125°C 

CERAMIC -55°Ct0 +150°C 

NOTE: Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tions at these limits is not intended and should be 
limited to those conditions specified in the DC Elec- 
trical Characteristics. 

10%, Vss = ov 



o 
S 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


lOL = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = - 200mA 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 






100 


mA 


All outputs open 



AC Electrical Characteristics Ta = 0° to 50°C, Vcc = 5V± 10%, Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


tWT 


t WCLK to i TIMCLK 






95 


nsec 




tWR 

*ZS 

tZK 


t WCLK tot TIMCLK 


90 




85 
120 


nsec 
nsec 
nsec 




4- CRCIZ tot SKPCLK 


CRCIZ pulse width 


tBS 


DOCE set up time w.r.t. 
4 DOCK 


20 






nsec 




tBH 
tDD 


DOCE hold time w.r.t. 
4 DOCK 


40 


. 


105 


nsec 
nsec 


CWE set high 


DIN to DOUT delay 



57 






o 
o 



SYMBOL 


PARAMETER 


MIN 


TY pi 


MAX 


UNIT 


CONDITION 


tDK 
*DW 

tic 
fsc 

*SR 
*SC 
t|N 


4DIN to 1 SKPCLK 

DlN P.W. to reset SKPCLK 


50 




120 

120 

120 

5.25 

85 

90 

90 


nsec 
nsec 
nsec 
nsec 
MHZ 
nsec 
nsec 
nsec 




4DOCKtc4CWE 


IDOCKtotCWE 


SHFCLK frequency 


tSHFCLKtotCRCOK 


tSHFCLKtoiCRCOK 


1 DOCK to i DIN 



Notes: 1. Typical values are for Ta = 25°C and Vqq = + 5.0V 



— ! 'ac K 



SHFCLK — ' ' — 'I I I II II I ' 




CRCOK 



read mode 



WD1 100-04 
Figure 3. Write Mode 



CRCIZ 



SKPCLK 



l ZK 



l ZS 



"~L 



DIN ^l nw fZ: 



WD1 100-04 
Figure 4. Initialize 



See page 725 for ordering information. 

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



58 



Printed in USA 



Western Digital 

WD1 100-05 Parallel/Serial Converter 



DESCRIPTION 

The WD 1100-05 Parallel/Serial Converter allows the user to 
convert a byte of data to a serial stream when writing to a 
disk or any serial device. Parallel dat a is entered via the D0- 
D7 lines on the rising edge of DCLK. A synchronous BYTE 
counter is used to signify that 8 bits of data have been 
shifted out and that the 8 bit latch is ready to be reloaded. 
The double buffering of the data permits another byte to be 
loaded while the previous byte is in the process of being 
shifted. 

The WD1 100-05 is implemented in NMOS silicon gate 
technology and is available in a 20 pin plastic or ceramic 
dual-in-line package. 






o 
o 



FEATURES 

SINGLE +5V SUPPLY 
DOUBLE BUFFERING 
BYTE STROBE OUTPUTS 
5 M BITS/SEC SHIFT RATE 
TRI-STATE OUTPUT CONTROL 
PARALLEL IN/SERIAL OUT 
20 PIN DIP PACKAGE 



DO C 

D2 \Z 

03 C 
D4 {^~_ 

D5 [Z 

D6 C 

D7|Z 

SHFCLK £Z 

v S s Q" 



Zl v C c 

] EN 
| NC 



] TEST 
] BDONE 
] DOUT 
| SHFCLK 
1 LD 



J WCLK 
I DCLK 



WD1 100-05 
Figure 1. Pin Connections 



D0-D7 



DCLK >- 



WCLK >- 




~y-^ 



+5V 



L 



TEST *~ 



BYTE 
COUNTER q 



LD 

T 



8 BIT SHIFT 
REG 



+5V 

u 



DOUT 



SHFCLK 
SHFCLK 



BDONE 



EN *~ 



->LD 



WD1 100-05 
Figure 2. Block Diagram 



59 






o 
o 



PIN NUMBER 


SYMBOL 


NAME 


FUNCTION 


1-8 
9 

10 
11 

12 

13 

14 

15 
16 

17 
18 
19 

20 


D0-D7 
SHFCLK 

VSS 
DCLK 

WCLK 

LD 


DATA0-DATA7 
SHIFT CLOCK 

GROUND 


8 bit parallel data inputs (bit 7 = MSB). 


Inverted copy of WCLK (pin 12) which is active when 
ENABLE (pin 19) is at a logic 0. 

GROUND. 

Active low input signal resets the BDONE (pin 16) latch. 
The low-to-high (trailing edge) clocks the input data into the 
internal 8 bit latch. 

The high-to-low (1) edge of this clock signal is used to shift 
the data out serially. The low-to-high (t) edge is used to up- 
date the internal byte counter (module 8). 

This active low signal indicates that the Byte Counter is be- 
ing preset to 1. Normally left open by the user. 


DATA CLOCK 


WRITE CLOCK 


LOAD 


SHFCLK 

DOUT 
BDONE 

TEST 

NC 

EN 

vcc 


SHIFT CLOCK 

DATA OUT 
BYTE DONE 


Delayed copy of WCLK (pin 12) which is active when EN 
(pin 19) is at a logic 0. 

Serial data output enabled by EN (pin 19). 

This output signal is forced to a logic 1 whenever 8 bits 
of data have been shifted out. BDONE remains in this 
state unless reset by the loading of another byte of 
data. 

This pin must be left open by the user. 

This active low signal enables DOUT, SHFCLK, 
SHFCLK, and BDONE outputs. When high, these out- 
put signals are in a high impedance state. 

+ 5 ± 10% power supply input. 


TEST INPUT 
No Connection 


ENABLE 

vcc 



DEVICE DESCRIPTION 

Prior to loading the WD1 100-05, it is recommended that 
00H (or FF) be loaded intojhe input buffers to ensure that 
DOUT is at a fixed level. EN (pin 19) is set to a logic to 
enable the device outputs. 

Data is entered on the D0-D7 input lines and is strobe d into 
the data latches on the rising edge of DCLK (pin 11). DCLK 
also resets BDONE (pin 16). The first BDONE that comes 
up simply means that the WD1 100-05 is ready to accept 
another byte of data and that the previous byte entered is in 
the process of being shifted out. If the BDONE is serviced 
prior to every 8th WRITE CLOCK pulse the output data will 
represent a contiguous block of the bytes entered. Due to 
the asynchronous nature of the WD1 100-05, the input data 
will be available in serial form at the output anywhere from 
8 to 16 write clock cycles later. 

Data is shifted out on the high-to-low (i) transition of the 
WCLK (pin 12). The low-to-high (t) transition of WCLK" in- 
crements a byte counter which in turn sets the BDONE 
signal high after 8 bits of data have been shifted out. The 
low-to-high transition of BDONE also causes the loading of 
the data buffer into the shift register. The data buffer is now 
ready to be reloaded with the next byte. 

The loading of the next byte automatically clears the 
BDONE signal. The entire process as outlined above is 
repeated. BDONE always needs to be serviced within 8 



WCLK cycles unless the next byte to be transmitted is the 
same as the previous byte. 

Four signals, BDONE, DOUT, SHFCLK, and SHFCLK, can 
be placed in a high impedance state by setting EN (pin 19) 
to a logic 1. Likewise, EN must be at a logic in order for 
these signals to drive any external device. 

The TEST pirns internally OR'ed with the counter output to 
produce the LD (pin 13) signal. This is used to inhibit the bit 
counter by ex ternal means for test purposes. It is recom- 
mended that TEST be left open by the user. An internal 
pullup register is tied to this pin to satisfy the appropriate 
logic level required for proper device operation. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°C to 50 °C 

Voltage on any pin with respect to Vss ■ ■ - - 0.2V to + 7.0V 

Power Dissipation 1 Watt 

STORAGE TEMPERATURE 

PLASTIC - 55 °C to + 125°C 

CERAMICS - 55°C to + 150°C 

NOTE: Maximum ratings indicate operation where perma- 
nent device damage may occur. Continuous opera- 
tions at these limits is not intended and should be 
limited to those conditions specified in the DC elec- 
trical characteristics. 



60 



DC Electrical Characteristics: T A = 0°Cto50°C; V cc = +5V ± 10%,^ = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




VOH 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


lOL = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


Iqh = -200 M A 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 






100 


mA 


All Outputs Open 






o 
o 



AC Electrical Characteristics: Ta = 0°Cto50°C; Vcc = +5 ± 10%;Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 





fwc 


WCLK frequency 






5.25 


MHZ 




tDW 


DCLK pulse width 


50 






nsec 






tDS 


Data set-up w.r.t. t DCLK 


30 






nsec 






tDH 


Data hold time w.r.t. t DCLK 


30 






nsec 






*DB 


IDCLKtolBDONE 






130 


nsec 


EN= 




*DO 


1 WCLK to DOUT 






130 


nsec 


EN= 




*SH 


J WCLK to * SHFCLK 






75 


nsec 


EN= 




tHS 


t WCLK tot SHFCLK 






70 


nsec 


EN= 




t\A/B 


tWCLKtotBDONE 


75 




180 


nsec 






tES 
*CL 


^ENtoBDONE, DOUT 
SHFCLK ACTIVE 






25 
50 


nsec 
nsec 






t WCLK to I LD 



NOTES: 1 . Typical Values are for Ta = 25°C and Vcc = + 5.0V 



WCLK 



-TLTLJl 

' L'dw 



7 8 12 3 4 5 



DCLK 



D7-DO 






'OBJ 



BONE C. 

LD — 



EN 



DOUT 



~T 



INVALID DATA 



SHFCLK [_" 

shfelkF 



an. 




u u 



WD1 100-05 
Figure 3. Functional Timing Diagram 



61 






o 
o 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is aissumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



. Printed m U S A 

62 



Western Digital 

WD1 100-06 ECC/CRC Logic 



DESCRIPTION 

The WD1 100-06 ECC/CRC logic chip gives the user of 
the WD1100 series of chips easy ECC or CRC imple- 
mentation. With proper software, it will provide single 
burst correction up to 8 bits and double burst detec- 
tion. The computer selected polynomial has been op- 
timized forWinchester5 1 /4" and 8" drives with sector 
sizes up to 512 bytes. 



FEATURES 

32 bit computer selected polynomial 
Single burst correction up to 8 bits 
Multiple burst detection 
Programmable correction/detection span 
CRC or ECC software selectable 
Data transfer rates to 5.25 Mbits/sec 
Serial check/syndrome bit processing 
128, 256, 512 byte sector sizes 
Single + 5V supply 
TTL, MOS compatible 
20 pin DIP package 






O 

o 
o 



R/Wfj^ 


^_y 

1 20 

2 19 

3 18 

4 17 

5 16 

6 15 

7 14 

8 13 

9 12 

10 11 


HJvcc 


rcpC 
wop I 


| WBS 

I RBS 

Idcss 


RDATr"* 


WDATl~ 


| EDOUT 


SEL.r- 


|dout 


ECCIZ |~^ 
NCl 


|FBD 

ICSE 


ECCEN (__ 

VssC 


( BS 


Irwcp 



SEL 



ECCIZ »~ 
DCSS *- 



R/W ■»- 



RCP »— O 
WCP *— O 



RDAT *>~-C 

WDAT »— O 

RBS >— O 

WBS*— O 



MUX 



CONTROL 



O-*- DOUT 



EDOUT 
CSE 
BS 

0-*~ ECCEN 
FBD 



RWCP 



SHIFT REGISTER 
D Q31 



— © 



WD1 100-06 Figure 1. 
PIN CONNECTIONS 



WD1 100-06 Figure 2. 
BLOCK DIAGRAM 



63 



WD1 10006 ECC/CRC DEVICE PIN DESCRIPTION 



PIN 
NUMBER 



1 



8 
9 

10 
11 



12 



13 



14 

15 
16 



PIN NAME 



READ/WRITE 



2 


READ CLOCK 
PULSE 


3 


WRITE CLOCK 
PULSE 


4 


READ DATA 


5 
6 


WRITE DATA 
SELECT 


7 


ECC INITIALIZE 



NO CONNECTION 
ECC ENABLE 



GROUND 

READ/WRITE 
CLOCK PULSE 



BYTE SYNC 



CLOCK S ELECT 
ENABLE 



SYMBOL 



R/W 



RCP 

WCP 

IRDAT 

WDAT 

SEL 



ECCIZ 



N/C 



FEEDBACK 



DATA OUTPUT 

EARLY D ATA 
OUTPUT 



ECCEN 



VSS 
RWCP 



BS 



CSE 



: BD 



DOUT 



EDOUT 



FUNCTION 



Input line used to select the data, clock and 
CRC/ECC strobe durin g read/write o perations. 
When low input signals WDAT, WCP, an d WBS 
are s elec ted. When high input signals RDAT, 
RCT 3 , and RBS are selected. 

Input pulse used by the internal shift registers 
to compute the 4 syndrome bytes. 

Input pulse used by the internal shift registers 
to compute the 4 check bytes. 

Serial data input during a read operation. 

Serial data input during a write operation. 

This input is used to select either the CRC or 
the ECC polynomial for error detec- 
tion/correction. SEL = ECC polynomial 
selected. SEL = 1 CRC polynomial selected. 

Input used to prese t al l the in t ernal shift 
registers. Output lines FBD, EDOUT, DOUT, and 
CSE will be in their inactive h igh st ate s. The 
first low going edge of either RDAT or WDAT 
signals the activation of all internal circuitry. 

No connection. 

When low, the ECC/CRC process is enabled. 
When high, this output signal indicates that the 
process is disabled. 

Ground 

Output clock pulse during read or write 
opera tions. The input clock pulses RCP and 
WCP are multiplexed on this output line for use 
by any support logic. 

The input signals RBS and WBS are gated with 
the appropriate clocks and multiplexed as an 
output on the byte sync line. Normally not used 
by the user. 

When high, this output indicates that the device 
is in the process of com puting the 
check/ syndrome bytes and that EDOUT and 
DOUT lines contain data information. When 
low, the device puts CRC or ECC check/syn- 
drome bits on the output data lines. 

The feedback line to the shift registers is 
brought out as an output line for test purposes. 
Normally left open by the user. 

Output data line carries data or CRC/ECC in- 
formation depending upon the state of DCSS. 

Unlatched output data line available 1 clock 
period earlier than DOUT. 



64 



WD1 100-06 ECC/CRC PIN DESCRIPTION (CONTINUED) 




PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


17 

18 
19 
20 


DATA/CHECK 
SYNDROME SELECT 


DCSS 

RBS 
WBS 

vcc 


Data or check/syndrome select input line. When 
high, data is output on the data lines; when low, 
CRC or check syndrome bits are output 
depending upon which polynomial is selected. 
DCSS goes low sometime between the last and 
the next to the last data byte transferred to/from 
the disk provided all set-up and hold-times have 
been met. DCSS must stay low for at least 2 
byte times when the CRC polynomial selected 
and it must stay low for at least 4 byte times if 
the ECC polynomial is selected. 

Input used to latch the state of DCSS during the 
read mode. 

Input used to latch the state of DCSS during the 
write mode. 

+ 5V ±10% 


READ BYTE 


WRITE BYTE 
+ 5V 



D 

.jk 

? 

o 

OS 



DEVICE DESCRIPTION 

To e nsure c orrect operation of the WD1 100-06 device, 
the ECCIZ line is strobed to preset the polynomial 
generator shift register, and reset the Data/Check- 
Syndrome select flip-flop. The 32 bit shift register 
string is preset to avoid all zero check bytes. The 
DCSS line is held high and appropriate signals are 
then applied to the rest of the inputs. Since most disk 
media use an Address mark of A1 (or M.S.B. set), 
advantage is taken of this feature to start off the 
ECC/CRC calculation on the data/ID fields automati- 
cally. The first active low going edge on the input 
data lin es releases the internal SET Flip-Flop. The 
ECCEN output line is set low indicating that the 
internal circuitry is ready to begin the computation of 
the ECC/CRC bytes. Immediately following the 
Address mark, data is supplied in a serial fashion. 

Sometime before the last byte of data and after the 
next to the last byte of data is transferred through 
this device, the DCSS line is set low. Since data is 
generally serialized/deserialized before/after process- 
ing by the WD1 100-06 device, the byte-sync pulses 
can be easily obtained from those devices marking 
the byte boundaries. The byte-s ync pulses are inter- 
nally ANDED with the RWCP line to ensure the 
smoot h transition of check/syndrome bytes on the 
DOUT output line only after the last bit of data has 
been entered into the device. A one bit time delay 
through a D Flip-Flop has been added on the DOUT 
line to deglitch this output line. 

During a WRITE operation, the input data stream is 
divided by the polynomial X32 + x28 + x26 + x19 
+ X"I7 + x10 + x2 + 1 and the 32 bit remainder ob- 
tained is used as the 4 check syndrome bytes. If the 
syndrome is zero, no errors occurred. Otherwise, the 
non-zero syndrome is used by a software algorithm to 
compute the displacement and the error vector 



within the bad sector. To protect the integrity of the 
ID field only a CRC check should be performed over 
this field. No attempt ought to be made to correct 
data in the ID field. The CRC polynomial imple- 
mented is the standard CCITT(X16 + X12 + X5 + 1.) 
Although either polynomial may be used for both 
fields, the use of the CRC polynomial for the ID fields 
is recommended since it only requires 2 bytes in- 
stead of 4. 

POLYNOMIAL SELECTION 

For disk media, polynomial selection has a signifi- 
cant influence on data accuracy. Fire code 
polynomials have been widely used on OEM disk 
controllers, but provide less accuracy than properly 
selected computer generated codes. 

For fixed, guaranteed correction and detection 
spans, data accuracy may be highly dependent on 
polynomial selection. Some polynomials, fire codes 
for example, are particularly susceptible to miscor- 
rection on common disk type errors, while others, 
computer generated polynomials for example, can be 
selected to be less susceptible, Computer generated 
codes do not have the pattern sensitivity of the fire 
code and the miscorrection patterns are more ran- 
dom in nature. 

More than 20,000 computer generated random 
polynomials of degree 32, each with 8 feedback 
terms, were evaluated in order to find the polynomial 
described in this specification. 

SELECTING THE CORRECTION SPAN 

The code described in this document can be used to 
correct up to 8 bits. 

Any correction span from 1 to 8 may be selected. 
However, for best data accuracy, the lowest correc- 
tion span should be used that meets the correction 



65 






o 
o 

■ 

o 



requirements for the disk drives supported. 

For most Winchester media, a 5 bit correction span is 
adequate. 

The correction span may have to be longer if the drive 
uses a read/write modulation method that maps a 
single media bit in error into several decoded bits in 
error. Examples of read/write modulation methods of 
this type would be GCR and 2,7 code. 

PROPERTIES OF THE POLYNOMIAL 

The following polynomial was computer selected for 
insensitivity to short double bursts, good detection 
span and 8 feedback terms. 

Forward polynomial is: 

X 32 + X 28 + x26 + x19 + X17 + X10 + x6 + X2 

+ 

Reciprocal polynomial is: 

X32 + x30 + x26 + x22 + x15 + X 13 + X6 + X4 

+ X0 

Properties* 

1. Maximum record length (r) = 526x8 bits (including 
check bits) 

2. Maximum correction span (b) = 8 bits 

3. Degree of polynomial (m) = 32 

4. Single burst detection span without correction = 
32 bits. (Detection span when the code is used for 
detection only) 

5. Single burst detection span with correction (d) — 
(Detection span when the code is used for correc- 
tion) 

= 19 bits for b = 5 and r = 526x8 
= 1 4 bits for b = 8 and r = 526x8 
= 20 bits for b = 5 and r = 270x8 
= 1 4 bits for b = 8 and r + 270x8 

6. Double burst detection span without correction — 
(Doule burst detection span when code is used for 
correction) 

= 3 bits f or b = 5 and r = 526x8 
= 2 bits f or b = 8 and r = 526x8 
= 4 bits f or b = 5 and r = 270x8 
= 2 bits f or b = 8 and r = 270x8 

7. Non-detection probability = 2.3E-10. 

8. Miscorrection probability— 

= 1 .57 E-5 f or b = 5 and r = 526x8 
= 1 .25 E-4 f or b = 8 and r = 526x8 
= 8.00 E-6 f or b = 5 and r = 270x8 
= 6.40 E-5 f or b = 8 and r = 270x8 

NOTE:* 

You should not use this polynomial for a record 
length or correction span beyond the maximum 
specified above. 



SOFTWARE REQUIREMENTS 

The software algorithm, developed by the user, uses 
the syndrome to detect an error, generate a correc 
tion pattern and a displacement vector or to deter- 
mine if uncorrectable. In the correction algorithm, a 
simulated shift register is used to implement the 
reciprocal polynomial. The simulated shift register is 
loaded with the syndrome and shifted until a correct- 
able pattern is found or the error is determined to be 
uncorrectable. Both forward and reverse displace- 
ments are computed. 

Either the serial or the parallel algorithm may be 
implemented by the user. In almost all cases the 
serial software algorithm is the most applicable. 
Additionally, 1K of table space is required if the 
parallel software algorithm is selected. It is assumed 
that the highest order bit of a byte is serialized and 
deserialized first. 

CORRECTION TIME PERFORMANCE 

All real time operations are performed with error cor- 
rection hardware. The software algorithms used get 
involved only after an error has been detected. 

The following correction times are for a serial type 
algorithm such as that used on the WD1001: 

a) Standard microprocessor = 30 to 60 milliseconds 

b) Bit slice = 6 to 12 milliseconds 

c) 8X300 (used on WD1 001) = 15 to 30 milliseconds 

DATA ACCURACY 

ERP (Error Recovery Procedure) strategies have a 
significant influence on data accuracy. An ERP 
strategy requires data to be re-read before applying 
correction and results in much better data accuracy. 
The WD1001 employs such a strategy. This strategy 
reduces the possibility of passing undetected erron- 
eous data by rereading until the error goes away, or 
until there has been a consistant error syndrome over 
two previous rereads. 

Another technique that can be used to give data a 
higher probability of recovery is write check: read 
back after write. Since write check affects per- 
formance, it should be optional. Alternate sector 
assignment and defect skipping are some of the 
other techniques that may be implemented by the 
user if so desired. 



66 



SELF-CHECKING WITH MICROCODE 

Periodic microcode and/or software checking is 
another approach that can be used to limit the 
amount of undetected erroneous data transferred in 
case of an ECC circuit failure. Microcode or software 
diagnostics could be run on subsystem power up 
and during idle times. These diagnostics would force 
ECC errors and check for the proper syndrome and 
proper decoding of the syndrome by the correction 
routine of the operational microcode. 

To do this, simply use a long bit in the READ and 
WRITE commands to the disk. This bit can then be 
used to suppress the transfer of check/syndrome 
bytes on the output data line by letting the DCSS line 
stay high during ECC TIME. The complete procedure 
is summarized below. 

1. WRITE: Pass all data to the disk and generate 4 
check bytes at the end of the data field. 

2. READLONG: Do not generate the syndrome, in- 
stead copy the 4 check bytes as data and pass 
them unaltered to the host. Now the host may in- 
duce errors anywhere in the data stream as long as 



the induced error does not exceed the correction 
span of the polynomial generator. 

3. WRITELONG: Write the data and check bytes 
supplied by the host to the disk. Prevent WD1100- 
06 from generating check bits by not asserting 
DCSS during transfer. No check bytes will be 
recorded. 

4. READ: Read data and generate the syndrome in a 
normal manner. The software algorithm can now 
be invoked to correct the induced error. 

To aid in detection of certain hardware failures, it is 
desirable to have non-zero check bytes for an all 
zeros record. This feature has been incorporated into 
the circuit defined in this specification. 






O 

o 
6 



67 






o 

o 

6 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under bias "C to 50°C 

Voltage on any pin with 

respect to Vss - 0.2V to + 7.0V 

Power dissipation 1 Watt 

Storaqe Temperature 

Plastic - 55°C to + 125°C 

Ceramic - 55°C to + 150°C 



NOTE: 

Maximum ratings indicate operation where per- 
manent device damage may occur. Continuous 
operations at these limits is not intended and should 
be limited to those conditions specified in the DC 
electrical characteristics. 



DC Electrical Characteristics Ta = 0°Cto50°C; Vcc = 


+ 5V ± 10%, Vss = 


OV 




SYMBOL 


PARAMETER 


MIN 


TYPi 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


|QL = 3.2 mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = - 200 M A 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 




75 


150 


mA 


All outputs open 













































ECCIZ PULSE WIDTH 




r/w ~X 


HIGH FOR READ 




LOW FOR WRITE X 




















ECCIZ. -*■ 




MZ 
>*- *IE 












ECCEN 








1 












RDAT 

WDAT *ST 


_^«- 


^"T HT 




















"*1 








-*— fCP 
















RCP I 
WCP J 


I 


' 


' 





























































AC Electrical Characteristics Ta = 0°Cto50°C; Vcc = 


+ 5V ± 10%, Vss 






SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


fCP 


Clock Frequency 






5.25 


MHZ 




tiz 


ECCIZ Pulse Width 


50 






nSec 




t|E 


ECCIZ 1 to ECCEN t 






100 


nSec 




tST 


R/WDAT Setup Time 


50 




1 Clock 
Period 


nSec 




tHT 


R/WDAT Hold Time 









nSec 





See page 725 for ordering information. 



68 



Western Digital 

WD1 100-07 Host Interface Logic 



DESCRIPTION 

The WD1 100-07 Host Interface Logic chip simplifies 
the design of a Winchester Hard Disk Controller 
using the WD1100 chip series. It does this by per- 
forming logic functions that would otherwise require 
considerable discrete logic. Additionally, there are 
signals provided for ECC implementation. 

The WD1 100-07 is implemented in NMOS silicon gate 
technology and is available in a 20 pin plastic or 
ceramic Dual-in-Line package. 



FEATURES 




• SINGLE +5V SUPPLY 


• WAIT SIGNAL GENERATION 




• TIMING CLOCK GENERATION 


o 
o 


• INDEX PROPAGATION 


■ 

o 


• CARD ACCESS CONTROL 


">J 


• COMPLIMENTS ECC ARCHITECTURE 




• 20 PIN DIP PACKAGE 





WCTi | 

WCL2 ^ 

RESET |Z 

SACEN CI 

AMDET d 

TIMCLKd 

RCLK C 



INDEX | 
LlNR Q 

VssC 



20 
19 

18 
17 
16 
15 
14 
13 
12 
11 



Zlvcc 

ZJWCLK 

Z2 cs 

Z] WHEN 
Zl RCP 

Zl RBS" 

ZJAMOOT 
ZICSAC 

Z]watt 
Z]lindex 



WD1 10007 Figure 1. 
PIN CONNECTIONS 



RD6 *• 



WR6 > 



WAEN >• 



cs >- 
SACEN ►■ 



WCLK 



RESET }*■ 

WR3 >> 



INDEX >- 



RCLK >• 



AMDET ► 



CONTROL 
LOGIC 



-^~ WAIT 



■**■ CSAC 



-5- 16 



-► TIMCLK 



1 



— D 



S 

LATCH 
R 



BYTE COUNTER 

AND 

DELAY 



LINDEX 



RBS 
RCP 



-► AMOUT 



WD1 100-07 Figure 2. 
BLOCK DIAGRAM 



69 



3 



o 
o 

6 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 
2 
3 
4 
5 

6 

7 

8 

9 
10 
11 

12 

13 

14 

15 

16 

17 

18 
19 

20 


WAIT CLEAR 1 


WCL1 


This input presets a WAIT latch to a non-WAIT 
condition on the falling edge. 
This input presets a WAIT latch to a non-WAIT 
condition on the falling edge. 
An input used to set TIMCLK & reset WAIT, 
AMOUT and RBS. 

This is an input signal that is used to enable 
card select for host access. 
An input that must go active when a 
DATA = A1(HEX) or clock = 0A(HEX) pattern is 
detected in the data stream 
An output used to provide reference timing sig- 
nals to SA100 type drives 
This input, the same as used to clock in data 
and clocks to the AM detector, is used to 
produce AMOUT. 

This input is provided by the drive once each 
revolution of the disk 

An input used to reset LINDEX. 
Ground 


WAIT CLEAR 2 


WCL2 


RESET 


RESET 


SELECT ADDRESS 
ENABLE 

ADDRESS MARK 
DETECT 

TIMING CLOCK 

READ CLOCK 


SACEN 


AMDET 

TIMCLK 
RCLK 


INDEX PULSE 


INDEX 
LINR 

vss 

LINDEX 


LINDEX RESET 
GROUND 
LATCHED INDEX 

WAIT 

CARD SELECT 
ADDRESS 
ADDRESS MARK 
DELAYED OUTPUT 
READ BYTE STROBE 

READ CLOCK PULSE 


An output that is INDEX delayed by one clock 
time. 

This output goes true when controller is inter- 
nally accessing data or has not accepted data 
from the host during a WRITE. 
An output that is the result of CS qualified with 
SACEN. 


WAIT 
CSAC 


AMOUT 

RBS 

RCP 


This output is a delayed version of AMDET. 

This output strobes once for each byte of READ 
data. Initialized by AMDET. 
This output is delayed from RCLK through prop- 
agation. Not normally used. 

An input that is used to enable the internal 

WAIT circuitry. 

An input from host that selects controller. 

This input is used to produce TIMCLK on low to 

high transitions. 

+ 5V ± 10% 


WAIT ENABLE 


WAEN 

CS 
WCLK 

vcc 


CARD SELECT 
WRITE CLOCK 

+ 5VDC 



DEVICE DESCRIPTION 



Upon power up or reset, WAIT, AMOUT, and RBS are 
reset and TIMCLK is set. This is the only interactive 
signal between the four sections of the chip. Each 
section will be described separately. 

Control Logic 

This section provides WATT (pin 12) and CS AC (pin 
13). WAIT is set in its active low state when WAEN 
(pin 1 7) is active low by the falling edge of CS (pin 1 8). 
WAIT is reset by the falling edge of either WCL1 or 
WCL2 depending on whether in a read or w rite mode. 
CSAC (pi n 13) is enabled by setting SACEN (pin 4) 
low after WAIT has been enabled. CSAC is reset by 
WCLIorWCLZ 



Timing Clock 

TIMCLK (pin 6) is a divided by sixteen version of 
WCLK (pin 19). It is used with SA1000 type drives. 

index Pulse 



Lindex (pin 1 1) is a delayed version of INDEX (pin 8). It 
remains high until reset by LINR (pin 9). 

Read Byte Sync 

RBS (pin 15) will go true on the e ighth ne gative going 
transition of RCLK (pin 7) after AMDET (pin 5) goes 
true. RBS will remain true for one clock cycle. 

Read Clock Pulse 

RCP (pin 16) is a delayed version of RCLK and is 
normally left open by the user. 



70 



Address Mark Delayed Output 

AMOUT (pin 14) is the same as AMDET delayed by 
two clock times. 

These circuits were developed to work with the other 
chips in the WD1100 series. They are used on the 
WD1001 the timing relationships must be observed. 

SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°Cto50°C 

Voltage on any pin with 

respect to Vss - 0-2V to + 7.0V 

Power Dissipation 1 Watt 

Storage Temperature Plastic - 55°C to + 125°C 
Ceramic - 55°C to + 150°C 



3 



o 
o 

■ 

o 

-si 



NOTE: 

Maximum ratings indicate operation when perma- 
nent device damage may occur. Continuous opera- 
tion at these limits is not intended and should be 
limited to those conditions specified in the DC Elec- 
trical Characteristics. 



DC Electrical Characteristics Ta = 0°Cto50°C; Vqc = +5V ± 10%;Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYpi 


MAX 


UNIT 


CONDITION 


V|L 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


lOL = 3.2mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = -200mA 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




ice 


Supply Current 






100 


mA 


All outputs open 



AC Electrical Characteristics Ta = 0°Cto50°C; Vcc = +5V ± 10%; 


vss = ov 






SYMBOL 


PARAMETER 


MIN 


TYPi 


MAX 


UNIT 


CONDITION 


fwc 


WCLK FREQUENCY 






5.25 


MHZ 




tew 


CSitoWAITi 




50 


160 


nSec 




tws 


WCL1I or WCL24 to WAITt 




170 


195 


nSec 




tsu 
tsc 


WAEN Setup Time 
SACEN4 to CSACt 


50 


5 


70 


nSec 
nSec 


WAIT TRUE 


tcs 


WCL1I or WCL2I to CSAC1 




45 


155 


nSec 


WAIT TRUE 


tWT 


WCLKttoTIMCLKt 






250 


nSec 




tLI 


INDEXItoLINDEXt 




50 


100 


nSec 




tLW 


LINRItoLINDEXi 




30 


100 


nSec 




tpc 


rclk; to RCP* 




30 


75 


nSec 




tRA 
tAM 


AMDET Setup Time 
AMDET4 to AMOUT4 


30 


50 
2 CLOCK 
CYCLES 


2 CLOCK 

CYCLES 

+ 45 


nSec 
nSec 




tBS 


RCLKi to RBSI 




8 CLOCK 
CYCLES 


8 CLOCK 

CYCLES 

+ 165 


nSec 




tRB 


RBS Period 




1 CLOCK 
CYCLE 









NOTE: Typical Values are for Ta = 25°C and Vcc = +5V 



71 



WAEN 



CS 



WAIT 



tsu- 



tew 



1 



*ws- 



WCL1 orWCL2 



u 



SACEN 



CSAC 



*SC 



t i 



*cs 



WCLK 



TIMCLK 



n_rTJTJTJT_rLn_rLrLrL_n_n_n 



twT- 



• fwc 



INDEX 

LINDEX 

DnTT 



t|_l- 



tLW-*^ 



U 



RCP 



RCLK 



AMDET 



AMOUT 



RBS 




*RA -*•» \*~ 



!<"Mam-»-j 



*BS- 



i-tRB*^ 



See page 725 for ordering information. 



72 



Western Digital 

WD1 100-09 Data Separator Support Logic 



GENERAL DESCRIPTION 

The WD1 100-09 Data Separator Support Logic, when 
used with the other chips in the WD1100 series, 
greatly reduces the external discrete logic required to 
design a Winchester hard disk data separator. The 
chip provides the pump signals to an external error 
amplifier, control signals to an internal bus and a 
special drive selection signal also to an internal bus. 

The WD1 100-09 is fabricated in NMOS silicon gate 




technology and is available in a 20 pin plastic or 
ceramic package. 

FEATURES 

• SINGLE +5V SUPPLY 

• DRUN GENERATION 

• DATA SEPARATION CONTROL SIGNALS 

• 20 PIN DIP PACKAGE 



6 





v-» 




dataC 




20 


Uvcc 


refQ 


2 


19 


U RGATE 


dinC 


3 


18 


Udmr 


oscLZ 


4 


17 


_JDRS4 


DRS1 C 


5 


16 


_J WRITE 


HIFROC 


6 


15 


^]DRS3 


DRS2|^ 


7 


14 


13 DS 


DRUNC 


8 


13 


HIWDAT 


DOUTQ 


g 


12 


Z3 down 


vssC 


10 


11 


I] up 




DMR 

DATA 

RGATE 

WDAT 




DATA 

SEPARATOR 

CONTROL 

LOGIC 




HIFRQ 



WD1 10009 Figure 1. 
PIN CONNECTIONS 



WD1 100-09 Figure 2. 
BLOCK DIAGRAM 



73 






o 
o 

6 



PIN 








NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


1 


READ DATA 


DATA 


Input that is used in DRUN generation. 


2 


REFERENCE 


REF 


An input that is 2 times the data rate that keeps 
the VCO on center frequency during non-read 
times. 


3 


DELAYED DATA IN 


DIN 


This input is a delayed version of DOUT. An 
external delay line is used. The signals are 
compared to provide pumps. 


4 


OSCILLATOR 


OSC 


An input from the external VCO that is used in 


5,7, 






pump development 


DRIVE SELECT 1- 


DRS1- 


Input signals indicating which drive has been 


15,17 


DRIVE SELECT 4 


DRS4 


selected. 


6 


HIGH FREQUENCY 


HIFRQ 


Output to controller microprocessor that in- 
dicates 16 ones or zeros have been entered on 


8 






the DATA line. 


DATA RUNNING 


DRUN 


Output that indicates to the controller 








microprocessor the completion of 16 ones or 








zeros on the data line. Used to switch from REF 








to DATA via firmware. 


9 


DATA OUT 


DOUT 


Output data line. Can be REF or DATA or WDATA 
depending on the condition of WRITE, DMR and 
RGATE. 


10 
11 


GROUND 


vss 

UP 


Ground 


UP PUMP 


An output that indicates REF is leading DATA. 








Goes to error amp. Open collector. 


12 


DOWN PUMP 


DOWN 


An output that indicates DATA is leading REF. 
Goes to error amp. Open collector. 


13 


WRITE DATA 


WDATA 


MFM Write data input. Output appears at DOUT 


14 


DRIVE SELECTED 


DS 


An output that indicates that one of four drives 


16 






have been selected. 


WRITE MODE 


WRITE 


This input is active during a write operation and 


18 


DATA MASTER 


DMR 


enables WDAT 


This input is used to provide time-out for DRUN 




RESET 




and HIFRQ in the event that 16 ones or zeros are 
not present. 


19 


READ GATE 


RGATE 


This input, usually provided by the controller 
microprocessor, places chip in read mode. 


20 


+ 5VDC 


vcc 


+ 5VDC ± 10% 



DEVICE DESCRIPTION 

The WD1 100-09 is divided into three sections. Each 
section will be described separately. 

Drive Select Logic 



DS (pin 14) w ill go active high if any input DSR1 
through DRS4(pins5, 7, 15, 17) are active low. 

Pump Logic 

Internal logic causes the UP (pin 11) and the DOWN 
(pin 12) to be set, initially to their inactive states. DIN 
(pin 3) is the delayed data developed by passing 
DOUT through a delay line. OSC (pin 4) is the output 
of the data separator VCO. Whichever reaches the 
pump logic first will determine whether UP PUMP or 
DOWN PUMP is produced. These signals are then 
sent to an external error amplifier and used for VCO 
correction. During a write, the DIN must be locked to 



a crystal oscillator clock and will hold the VCO on 
frequency. 

Data Separator Control Logic 

Read Mode 

In order to prevent the external VCO from locking 
onto a harmonic of its operating frequency, REF (pin 
2) is provided with a si gnal twic e the data rate that is 
crystal controlled. With WRITE (pin 6) and RGATE (pin 
19) inactive, this signal will appear at DOUT (pin 9). 
This signal is applied to the pump logic (see above). 

The switching function is initiated immediately after 
RGATE goes true. DMR (pin 18) will be set active as a 
result of high frequency pulses applied to an external 
one shot whose pulse width is such that its output is 
a single stretched pulse. The high frequency pulses 
are applied to the DATA (pin 1) line and a fter 16 
consecutive pulses, DRUN (pin 8) and HIFRQ (pin 6) 



74 



go true. At this point REF is switched out and the 
DATA stream is switched in and appears at DOUT. 
DRUN is reset when RGATE goes inactive and 
HIFRQ goes inactive when DMR goes inactive. 



Write Mode 



When WRITE (pin 16) goes active, REF is switched 
out and WDAT (pin 13) will appear at DOUT. Since 
WDAT is a crystal controlled signal (usually the MFM 
write data); the VCO is held locked and will not drift 
(see pump logic above). 






o 

o 

6 

CO 



READ MODE 



DMR 



DATA 



DRUN 



RGATE 



HIFRQ 



-is- 



JUuTrirLjimiiRJinjn^^ 

♦dd ■*-! •-*■ ' 



41- 



*HD 



*DR 



-f fr- 



H«*- 



-REF- 



HH-<- 



DATA- 



-»-!-« REF 



DOUT 



_jwuwiJiMinrin^^ 

-*i h— fRE 



WRITE 



WRITE MODE 
DMR 



DATA 



DRUN 



HIFRQ 



WRITE 



■REF- 



-***- 



■DATA- 



DOUT 



¥innnnnnnn_rLn_rui 



rLTLJ^JTJUl 



AC Electrical Characteristics Ta = 0°Cto50°C; Vqc = +5V ± 10%;Vss = OV 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


tDD 
tDR 
tHD 

fRE 


DATA* to DRUN1 




2 TIMES 
DATA RATE 


170 
90 
90 
10 


nSec 
nSec 
nSec 

MHz 




RGATE* to DRUNt 


DMRItoHIFRQt 
REF frequency 



75 



3 

a 



o 
o 

■ 

o 

CO 



SPECIFICATIONS 

ABSOLUTE MAXIMUM RATINGS 

Ambient Temperature under Bias 0°Cto5Q°C 

Voltage on any pin with 

respect to Vss - 0.2V to + 7.0V 

Power Dissipation 1 Watt 

Storage Temperature Plastic -55°Cto + 125°C 
Ceramic - 55° C to + 150°C 



NOTE: 

Maximum ratings indicate operation when perma- 
nent device damage may occur. Continuous opera- 
tion at these limits is not intended and should be 
limited to those conditions specified in the DC Elec- 
trical Characteristics. 



DC Electrical Characteristics Ta = 0°Cto50°C; V<x = +5V ± 10%; Vss = 0V 



SYMBOL 


PARAMETER 


MIN 


TYP 1 


MAX 


UNIT 


CONDITION 


VlL 


Input Low Voltage 


-0.2 




0.8 


V 




V|H 


Input High Voltage 


2.0 






V 




vol 


Output Low Voltage 






0.4 


V 


lOL = 3.2mA 


VOH 


Output High Voltage 


2.4 






V 


lOH = ~ 200^A 


vcc 


Supply Voltage 


4.5 


5.0 


5.5 


V 




>cc 


Supply Current 






100 


mA 


All outputs open 



NOTE: UP and DOWN are open collector outputs and provide 12mA IrjL @ -5V. 
See page 725 for ordering information. 



76 



Printed in U S.A 



WESTERN DIGITAL 

CORPORATION 

WD1010 Winchester Disk Controller 




FEATURES 

Compatible with most 8- and 16-bit processors 

Data rate up to 5 Mbits per second 

Multiple sector read/write commands 

Unlimited interleave capability 

Automatic formatting 

Software selectable sector size 

(128, 256, 512, or 1024 bytes per sector) 

CRC generation/verification 

Automatic retries on all errors 

Automatic restore on seek errors 

Single +5V supply 

Provision for external ECC capability 









BCSC 


1 ^ 40 


DVCC 


BCRL 


2 39 


DRC 


INTRQC 


3 38 


URG 


NCC 


4 37 


URD 


MRL 


5 36 


JBDRQ 


REC 


6 35 


HBRDY 


WEE 


7 34 


HDRUN 


CSC 
AOC 


8 




33 


DRWC 
HSC 


9 




32 


A1C 


10 




31 


3 TK000 


A2C 


11 




30 


HWF 


D7 C 


12 




?q 


3 INDEX 


D6C 


13 28 


HDRDY 


D5C 


14 27 


USTEP 


D4'C 


15 26 


3 DIR 


D3C 


16 25 


3 WC 


D2C 

D1 C 
DOC 


17 24 

18 23 

19 22 


]WG 


3 EARLY 


DLATE 


VSSC 


20 21 


3 WD 


F 


'IN CONNECTION* 





APPLICATIONS 

• Seagate ST506, ST51 2 

• Shugart SA1000, SA1 100, SA600 

• Tandon 600 Series 

• Texas Instruments 506 

• RMS 500 Series 

• Quantum Q2000 Series 

• Miniscribe 

. . . and others 

DESCRIPTION 

The WD1010 is a MOS/LSI device designed for use 
with the drives listed above as well as other drives 
compatible with the SA1000 or ST506 interface. The 
controller requires only a single + 5 volts supply. It is 
designed to operate with an external sector buffer 
memory and to interface directly with TTL logic. 

The WD1010 is fabricated 
technology and is available 
ceramic or plastic package. 

FUNCTIONAL DESCRIPTION 

The WD1010 is software compatible with the WD1000 
controller board. Programming is very similar to that 
of the Western Digital FD179X floppy disk controller. 

Data bytes are transferred to or from the buffer every 
1.6/isec, with a 5Mbit/sec drive. The buffer may be 
either the Western Digital WD1510 128x9 FIFO 
memory (Fig. 1) or a combination of a 256x8 static 
RAM and a 9 bit resettable counter (Fig. 2). The 
WD1010 generates control signals to minimize ex- 
ternal gating. Buffer to processor transfers are made 
via programmed I/O or DMA. The controller also 
generates handshake signals to control DMA 
operations for multiple sector transfers. The WD1010 
interfaces to the Western Digital DM1883 and other 
DMA controllers. 



in NMOS silicon-gate 
in a 40-pin, Dual-in-line 



o 

o 
o 



77 



TABLE 1. INTERFACE SIGNALS 



PIN NUMBER 



SYMBOL 



PIN NAME 



FUNCTION 



12-19 
6 



9-11 

8 

3 

5 

1 

35 

2 

36 

40 
20 
4 
21 

25 

24 

23,22 

37 

39 

38 

39 

27 

26 

28 

30 

31 



D7-D0 
RE 

WE 

A0-A2 
CS 

INTRQ 
MR 



BCS 
BRDY 



BCR 
BDRQ 

vcc 
vss 

NC 
WD 

WC 

WG 

EARLY, LATE 

RD 

RC 

RG 

DRUN 

STEP 

DIR 

DRDY 

WF 

TK000 



Data 7 - Data 
READ ENABLE 

WRITE ENABLE 

ADDRESS 0- 
ADDRESS 2 
CHIP SELECT 

INTERRUPT 
REQUEST 
MASTER RESET 

BUFFER CHIP 
SELECT 
BUFFER READY 

BUFFER COUNTER 
RESET 

BUFFER DATA 

REQUEST 

+ 5 volt 

GROUND 

NO CONNECTION 

WRITE DATA 

WRITE CLOCK 

WRITE GATE 

EARLY, LATE 

READ DATA 

READ CLOCK 

READ GATE 

DATA RUN 

STEP PULSE 

DIRECTION 

DRIVE READY 

WRITE FAULT 

TRACK 000 



Eight bit bidirectional bus used for transfer of 
commands, status, and data. 

Tristate bidirectional line, used as an input for 

reading the task register and an output when 

WD1010 is reading the buffer. 

Tristate bidirectional line used as an input for 

writing into the task register and as an output 

when the WD1010 is writing to the buffer. 

These three inputs select the register to 

receive/transmit data on D0-D7. 

A logic low on this input enables both WE and 

RE signals. 

Active high output which is set to a logic high in 

the completion of any command. 

A logic low in this input will initialize all internal 

logic. 

Active low output used to enable reading or 
writing of the external sector buffer. 
This input is used to inform the controller that 
the sector buffer is full or empty. 

Active low output that is strobed by the WD1 01 
prior to read/write operations. 
This output is set to initiate data transfers 
to/from the sector buffer. 
+ 5V - 5% Power supply input. 
Ground. 

This pin must be left open by the user. 
This output contains the MFM clock and data 
pulses to be written on the disk. 
4.34 or 5.0 MHz clock input used to derive all 
internal write timing. 

This output is set to a logic high before writing 
is to be performed on the disk. 
Precompensation outputs used to delay the WD 
pulses externally. 

Data input from the Drive. Both MFM clocks and 
data pulses are entered on this pin. 
A normal square wave clock input derived from 
the external data recovery circuits. 
This output is set to a logic high when data is 
being inspected from the disk. 
This input informs the WD1010 when a field of 
one's or zeroes have been detected. 
This output generates a pulse for the stepping 
motor. 

This output determines the direction of the 
stepping motor. 

This input must be at a logic high in order for 
commands to execute. 

An error input to the WD1010 which indicates a 
fault condition at the drive. 
An input to the WD1010 which indicates that 
the R/W heads are positioned over the outer- 
most cylinder. 



78 



TABLE 1. INTERFACE SIGNALS 



PIN 
NUMBER 


SYMBOL 


PIN NAME 


FUNCTION 


29 


INDEX 


INDEX PULSE 


A logic high on this input informs the WD1010 
when the index hole has been encountered. 


33 


RWC 


REDUCED WRITE 
CURRENT 


This output can be programmed to reduce write 
current on a selected starting cylinder. 


32 


SC 


SEEK COMPLETE 


This input informs the WD1010 when head 
settling time has expired. 



PROCESSOR INTERFACE DESCRIPTION 

The WD1010 controller interfaces to a host or I/O 
processor via an 8 bit bidirectional data bus. The 
buffer memory is also connected to the data bus. The 
WD1010 is designed for use with buffer memory and 
external bus transceivers. One anticipated system 
configuration is shown in Figure 1. In this system, 
the processor starts a disk operation by writing task 
information into the register file in the controller. The 
task information includes the disk cylinder, head, 
sector numbers, drive number, track number for start 
of write precompensation, sector size, and number of 
sectors to be transferred. After the task information 
has been written, the processor writes the command 
into the command register. In the case of a write 
sector command, the processor can then read the 
controller status register to inspect the buffer data 
request flag, and write data into the buffer memory. 
When the buffer becomes full, it activates the BRDY 
input of the controller. The controller then deac- 
tivates the buff er data request (BDRQ) line and ac- 
tivates the BCS line. The buffer chip select (BCS) line 
is used both for buffer _memory_control and for 
disabling the data bus, RE and WE buffers. The 
controller thus has a direct bus to the buffer memory 
which is isolated from the processor data bus. When 
the buffered data is transferred to disk and the buffer 
memory is empty, the controller enables the tristate 
buffers, thus reconnecting the two busses. The 
processor can then write more data into the buffer 
memory. 

The WD1010 disk controller generates control sig- 
nals for RAM-counter control, data bus control, ECC 
processor and DMA control. 

TABLE 2. TASK REGISTER FILE 



A2 


A1 


AO 


READ 


WRITE 











Data 


Data 







1 


1 



Error Flags 
Sector Count 


Write PrecompCyl. 
Sector Count 





1 


1 


Sector Number 


Sector Number 


1 
1 
1 





1 



1 



Cylinder No. Low 
Cylinder No. High 
SDH 


Cylinder No. Low 
Cylinder No. High 
SDH 


1 


1 


1 


Status 


Command 



IP 


LBLE 


3. SDH REGISTER 






SECTOR 


SECTOR 


DRIVE* 


HEAD* 


EXTENSION 


SIZE 


NUMBER 


NUMBER 


BIT 7 


6 


5 


4 


3 


2 


1 





1 = ECC 


1 


1 


128 byte data field 


= CRC 








256 byte data field 







1 


51 2 byte data field 




1 





1024 byte data field 



'Drive Number and Head Number must be externally 
decoded and latched. 



DRIVE INTERFACE DESCRIPTION 

The WD1010 disk controller is designed to interface 
to SA1000 Winchester disk drives. Winchester drives 
with similar interfaces, such as the Seagate 
Technology ST506, can also be controlled. 

The WD1010 contains MFM encoder/decoder, ad- 
dress mark detector, and high speed shift register 
circuitry. Signals are provided to control write 
precompensation and write splice avoidance. Ex- 
ternal circuitry must provide a phase locked MFM 
read clock and high frequency detection. Figure 1 
shows a typical controller-drive interface for a system 
with two Winchester disk drives. 

WD1010 inputs are TTL compatible unless otherwise 
noted. WD1010 outputs will drive one TTL unit load. 



STATUS BIT DESCRIPTION 

Busy — Active when controller is accessing the disk. 
Activated by start of command (writing into com- 
mand register). Deactivated at end of all except read 
sector. For read sector, Busy is deactivated when a 
sector of data has been transferred to buffer. 

Drive Ready — Normally reflects the state of DRDY 
pin. After an error interrupt, the state of DRDY is 
frozen until the status register is read. The DRDY bit 
then reflects the state of the DRDY pin. An interrupt 
is generated when reset. 

Write Fault — Reflects the state of the WF pin. An 
interrupt is generated when set. 



a 
o 
o 



79 



o 

o 

T- 

Q 



Seek Complete — Reflects the state of the SC pin. 

Data Request — Reflects the state of the BDRQ pin. 
When active, indicates that a buffer data transfer is 
desired. The data request flag is used for pro- 
grammed I/O while the BDRQ pin is used for DMA 
controlled I/O. 

Command in Progress — Indicates that a command 
is in progress. 

Error — Indicates that a bit in the error register has 
been set. 

ERROR BIT DESCRIPTION 

Bad Block — A bad block address mark has been 
detected when trying to read or write that sector. 

Data Field CRC Error — An error in the data field has 
been detected. The sector can be re-read to attempt 
recovery from a soft error. The data contained in the 
buffer can be read but contains errors. 



ID Not Found — Occurs when cylinder, head, sectoi; 
or size parameters cannot be found after 16 index 
pulses have been encountered. 

TK000 Error — Occurs when track not found in a 
Restore command after 1024 stepping pulses. 

Aborted Command — Set if command was started 
and one of the following conditions occurred: 

1. Drive not ready 

2. Write fault 

3. Seek complete not active within 16 index pulses 

4. Illegal command code 

Data AM Not Found — During a read command, 
the ID field for the desired sector has been 
found, but the data field address mark was not 
found. The data AM should be found within 15 
bytes after the ID field. Refer to Figure 3 for 
track format. 



I 



REPEATED N TIMES 



GAP 

4 

(4E) 



GAP 3 
(4E) 



14 BYTES 
(00) 



I 

H«-J 200 



(A1) (IDENT) 



CYL 
LOW 



SH 



SEC 



ID FIELD 



200 nS. MIN. INDEX PULSE 



WRITE GATE 



CRC 
-2- 



12 

3B !bytes 



(00)' 



j (00) 



(AD 



(FB) 



DATA 
FIELD 



CRC 
■2- 



DATAFIELD- 



— u 

3 BYTES f 
(00) I 

i ^ 



NOTE: 

1) When MSB of head byte = 1, bad block is 
detected. 

2) Write Gate turn-on is 3 bytes after the ID 
field's CRC bytes. 

3) Write Gate turn-off 
Field's CRC bytes. 



is 3 bytes after the Data 



4) 12 bytes of zeroes are re-written on a Data 
Field update. 

5) The 2 LSB's of the IDENT byte are used for 
Cylinder high. These values are: 

FF = to 255 cylinders 
FF = 256 to 511 cylinders 
FC = 512 to 767 cylinders 
FD 768 to 1023 cylinders 

6) GAP 3 length is programmable and may range 
from 3 bytes to 255 bytes. 

FIGURE 3 
TRACK FORMAT 



TABLE 4. STATUS/ERROR REGISTERS 





STATUS 


ERROR 


BIT 


REGISTER 


REGISTER 


MSB 7 


BUSY 


Bad Block 


6 


DRIVE READY 


Data Field CRC 


5 


WRITE FAULT 


Reserved ( = 0) 


4 


SEEK COMPLETE 


ID Not Found 


3 


DATA REQUEST 


Reserved ( = 0) 


2 


RESERVED ( = 0) 


Aborted Command 


1 


COMMAND IN 
PROGRESS 


TKOOO Error 


LSBO 


ERROR 


Data AM Not Found 



80 



TABLE 5. COMMAND REGISTER 





MSB 














COMMAND 


7 


6 


5 


4 


3 


2 


1 





RESTORE 











1 


R3 


R2 


R1 


RO 


SEEK 





1 


1 


1 


R3 


R2 


R1 


RO 


READ SECTOR 








1 





D 


M 








WRITE SECTOR 








1 


1 





M 








SCAN ID 





1 




















WRITE FORMAT 





1 





1 



















£ 


D = 1 for DMA; for Programmed I/O 


Q 


M = 1 for multiple sector read or write 




R3 R2 R1 RO = 0000 


Step time = 20 us 


0001 


Step time = .5 ms 


o 


0010 


Step time = 1.0 ms 




0011 


Step time = 1.5 ms 




1111 


Step time = 7.5 ms 





for 5 MHz write clock 



2XDR 



H 
O 
S 

T 

P 
R 
O 
C 

E 
S 
S 

o 

R 



DATA 



AODR 



S 
Y 

S R 
T A 

E 
M 



M 




WINCHESTER DRIVE 



WRITE DATA 

READ DATA 

DRIVE SEL 

STEP 

DIRECTION 

READY 

WRITE FAULT 

TRACK 000 

INDEX 

SEEK COMPLETE 

RWC 

HEAD NR 

WRITE GATE 



DATA 



ADDR 



DAISY CHAIN TO 
NEXT DRIVE 



(HOLDS DRIVE AND HEAD 
SELECTS) 



DATA LATCH 



FIGURE 1. 



81 



o 

O 
O 



H 
O 
S 

T 

P 
R 
O 
C 

E 
S 
S 

o 

R 


RE 

WE 

DATA 

ADDR 
INT 
MR" 










RE 
WE 
D0-D7 

BCR 

WD1010 

BRDY 

BC3 

CS 

A0-A2 

INTRQ 

MR 


K , 






, K , 




. ,8 




U<p 




















A 


















C Q 
TC 




ke we 




L -i-^r> 


ADDR D 
CS 










































DECODE 


Oi 








rt 


























/2 








/ 






































1MM 







TO DATA LATCH 



FIGURE 2. 



See page 725 for ordering information. 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to chango 
specifications at anytime without notice. 



82 



Printed in USA 



WESTERN DIGITAL 

CORPORATION 



feS 



WD1011 Winchester Data Separator Device 



FEATURES 

4.34 OR 5.0 MBIT/SEC DATA RATE 
INTERNAL CRYSTAL OSCILLATOR 
SINGLE +5V SUPPLY 
FM OR MFM OPERATION 
COMPATIBLE WITH THE WD1010 
WRITE CLOCK GENERATOR 
HIGH FREQUENCY DETECTION 



GENERAL DESCRIPTION 

The WD1011 Winchester Data Separator has been 
designed to replace the complex analog/digital cir- 
cuitry required for data recovery by Winchester disk 
drives. Directly interfacing to the WD1010 Winchester 
Controller device, an on-chip crystal oscillator allows 
operation of 4.34 Mbit/sec or 5.0 Mbit/sec transfer 
rates. In addition to data recovery, the device 
provides Write Clock signals for the WD1010 as well 
as high frequency detection for pre-amble search. 
Output levels on data pins swing close to the supply 
rails for increased noise immunity and to minimize 
layout restrictions. 

The WD101 1 operates from a single 5 volt supply and 
is available in a 16 pin plastic or ceramic Dual-in-Line 
package. 



v-/ 


n 


1 16 


H 


IZ 


2 15 


=) -*\ 


lz 

rj 


^^ 11 Z] 


V-^iZ 


7 10 


Zl 


n. 


8 9 


Zl 


PIN DESIGNATION 






See page 725 for ordering information. 



83 



a 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to chango 
specifications at anytime without notice. 



Printed in USA 

84 



WESTERN DIGITAL 

CORPORAT/ON 



fe£ 



WD1012 Write Precompensation Device 



FEATURES 

• DIRECT INTERFACE TO THE WD1010 

• 12 NS. TYP. DELAY FROM EARLY 

• PROVIDES TIMCLK FOR SA1000 TYPE DRIVES 

• SINGLE +5V SUPPLY 

• TTL COMPATIBLE INPUT/OUTPUTS 

• COMPANION CHIP TO THE WD1011 DATA 
SEPARATOR 

GENERAL DESCRIPTION 

The WD1012 Write Precompensation device provides 
delayed data necessary for inner cylinder recording 
on Winchester disk drives. It is a companion chip to 
the Western Digital WD1010, utilizing signals from 
both the WD1010 and WD101 1 data separator device. 
The WRITE DATA output, as well as EARLY, LATE, 
and RWC are applied to produce a pre-determined bit 
shift. Assertion of EARLY or LATE will cause a 12 ns. 
typ. shift of data based upon the precompensation 
algorithm internal to the WD1010. In addition, a 
divide-by-sixteen timing clock output is available for 
use by the SA1000 and other drives requiring a 
TIMCLK input. 

The WD1012 operates from a single 5 volt supply and 
is available in a 14 pin plastic or ceramic package. 




3 
O 

o 

ro 



See page 725 for ordering information. 



85 



a 

o 
10 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



86 



Printed in U S A 



WESTERN DIGITAL 

CORPORAT/ON 



WD1014 Buffer Manager/Error Correction Device 



FEATURES 

• DIRECT INTERFACE TO THE WD1010 

• 32 AND 56 BIT ECC POLYNOMIALS 

• 128, 256, 512, OR 1024 BYTE SECTORS 

• BUFFER SIZE UP TO 32K BYTES 

• CONTROL FOR 4 DRIVES/8 HEADS EACH 

• AUTOMATIC RETRY ON ECC ERRORS 

• TRANSPARENT ECC CORRECTION 

• MULTI-SECTOR READ/WRITE CAPABILITY 

• DMA OR PROGRAMMED I/O OPERATION 

• 8-BIT TRI-STATE DATA BUS 

• EXECUTES 11 MACRO-COMMANDS 

• SINGLE + 5V SUPPLY 



GENERAL DESCRIPTION 

The WD1014 is a single chip Buffer Manager/ECC 
device designed for use with the Western Digital 
Corp. WD1010 Hard Disk Controller. The device 
implements all of the logic required for a variable 
length sector buffer, ECC correction and Host in- 
terface circuitry. Use of the BMEC greatly reduces 
the complexity of the interface design, device count, 
board size requirements and increases system 
reliability. 

The WD1014 operates from a single + 5V supply and 
is available in a 40 pin plastic or ceramic Dual-in-Line 
package. 





o 



PIN DESIGNATIONS 



87 



PIN 
NUMBER 



1-8 

9 

10 
11 
12 

13-15 

16 

17 



18 


CLK 


19 


HDS 


20 


vss 


21-23 


XA2-0 


24 


BCINC 



25 



26 



SYMBOL 



DAL7-0 

CS 

RE 
WE 
MR 

A0-2 

INTRQ 

DRQ 



BBSY 



BRDY 



27 


ALE 


28 


RCS 


29 


XRE 


30 


XWE 


31 


XCS 


32-39 


AD7-0 



40 



DESCRIPTION 



vcc 



Data Access Lines. Commands, status, and data to and from buffer are 
transferred over this tristate bidirectional data bus controlled by the host. 
DAL7 is MSB. 

Chip Select must be active for all communications with the BMEC. 

Read Enable. For reading data and status information from the BMEC. 

Write Enable. For writing commands and data to the BMEC. 

Master Reset. Initializes the BMEC and clears the status flags when ac- 
tivated. 

Address inputs. Used to select task file registers and data buffer. A2, A1, A0 
= 000 selects buffer. A2 is MSB. 

INTerrupt ReQuest. Activated whenever a command has been completed. It 
is reset when the status register is read, or when a new command is loaded 
via DAL7-0. 

Data ReQuest. Set whenever the buffer contains data to be read by the host 
or is awaiting data to be written by the host. 

Clock signal input used for all internal timing. 

Head & Drive Select for setting HSO-3 and DS1-4. 

GROUND 



These address lines are used to address the disk controller when XCS = 0. 
Buffer Counter INCrement. Increments the external buffer counter. Each 
negative transition is a one byte count. 

Buffer BuSY. Signals the BMEC that the buffer is being accessed by the 
disk cont roller . It is also used to control ADO-7 bus switching and tristate 
XWE, and XRE when it is active. 

Buffer ReaDY output. Signals the disk controller when the buffer memory is 
ready for controller data transfers. It is active when the buffer memory is 
full or empty. 

Address Latch Enable. Used to set the external buffer address whenever 
the buffer is not being accessed by the WD1010 processor. 

Ram Chip Select. Asserted when the BMEC or host accesses the external 
buffer. 

Tristate line activated only when BBSY = high. When XCS is low, in- 
format ion i s read from the selected WD1010 task files registers. 
When RCS is low, data is read from the buffer. 

Tristate line activated only when BBSY = high. When XCS is low, command 
or task file information is written into the disk controller. 

When RCS is low data is written into the buffer. 

This Chip Select is used to access the disk controller. 

Address or Data bus shared by the buffer, BMEC and the WD1010. While 
ALE is active a new buffer address is latched in an external counter, where 
AD7 = A14 and AD0 = A7. This allows buffer sizes from 128 bytes to 32K 
bytes. 

+ 5 ± 5% volt power supply. 



FUNCTIONAL DESCRIPTION 

The BMEC is designed to interface directly with 
industry standard static RAM chips and common 
TTL/LS latches and counters. The sector buffer, an 
integral part of the WD1010 system architecture, is 
addressed by a multiplexed data/address bus (AD0-7), 



which is also shared by the WD1010 and drive/head 
control latches. The WD1014 manages the external 
sector buffer so that it can support all WD1010 sector 
sizes in single and multiple sector operations. All 
buffer control signals required by the WD1010 are 
produced by the BMEC so that no external logic is 
required to interface the WD1010 to the BMEC. 



88 



During sector reads and writes, the BMEC produces 
an Error Correction Code (ECC) as data is transferred 
to and from the buffer. The user may select either a 
32 or 56 bit polynomial depending upon his needs. 
Errors are detected and corrected without in- 
tervention by the host. The BMEC controls all retries 
on data ECC errors for the host as well. Corrected 
errors are reported as a status to the host. Un- 
correctable errors are reported by setting the error bit 
in the status register with the appropriate descriptor 
bit set in the error register. 

TASK FILE 

The task file is a set of registers which contain 
commands, status, track, sector and other task in- 
formation. Nine registers are accessed via A2 to AO 
during read and write modes. Depending on the 
command from the host and the status of the 
system, the proper information is stored to or read 
from the task file. 



A2 A1 AO 


READ 


WRITE 


1 1 1 


Status 


Command 


1 


Error flags 


Write Precomp 
Cylinder 


1 


Sector Count 


Sector Count 


1 1 


Sector Number 


Sector Number 


1 


Cylinder Number 


Cylinder Number 




(low) 


(low) 


1 1 


Cylinder Number 


Cylinder Number 




(high) 


(high) 


1 1 


SDH* 


SDH* 



*S D H bytes specifies sector size, drive 
number and head number. 

The SDH register is coded as follows: 

Bit 7 (MSB) is set for a 7 byte sector extension (used 

for ECC bytes). 

Bits 6 and 5 contain the sector size. 

The possible sector sizes and their selection codes 

are: 



BIT 6 


BIT 5 


SECTOR SIZE 


1 



1 


1 

1 



128 byte data field 
256 byte data field 
512 byte data field 
1024 byte data field 



Bits 4 and 3 specify Drive Number. These bits are 
decoded internally and latched externally to perform 
the select function. 
Bits 2, 1 and specify Head Number. 

COMMAND REGISTER 

The command register is accessed by writing into 
register 7. All other task information should be 
loaded into the task file before loading the command 



register. Command execution starts immediately 

after the command register is loaded and sub- ^ 

sequent register loads are ignored until the com- q 

mand is done. The commands are as follows: ~± 





BIT CODE 


COMMAND 


MSB 7 6 5 4 3 2 10 


Restore 


1 R3 R2 R1 Ro 


Seek 


1 1 1 R3 R2 R1 Ro 


Read Sector 


1 D M E 


Write Sector 


1 1 M E 


Scan ID 


10 


Write Format 


10 10 


Read Copy 


1 1 M E 


Write Copy 


10 1 1 M E 


Read Long 


1 1 D 1 E 


Write Long 


1 1 1 D 1 E 


Set Parameters 


1 10 10 



D = 1: 
D = 0: 
M = 1 
E=1: 
E = 0: 
R3 R2 R1 



Interrupt for DMA mode 
Interrupt for programmed I/O mode 
Multiple Sector Read or Write 
Select 56 bit ECC polynomial 
vSelect 32 bit ECC polynomial 



R0 = 0000 
0001 
0010 
0011 



Step time = 20hs 
Step time = .5ms 
Step time = 1.0ms 
Step time = 1.5ms 



1111 Step time = 7.5ms 

for 5 MHz write clock 

THE STATUS AND ERROR REGISTERS 

The Status Register indicates to the host the status 
of the system. If the Error bit in the Status Register is 
set, one or more bits in the Error Register will be set. 
The meaning of the these bits is shown below: 



BIT 


STATUS 


ERROR 




REGISTER 


REGISTER 


MSB 7 


Busy 


Bad Block Detect 


6 


Drive ready 


Uncorrectable 


5 


Write fault 


CRC Error — ID 
Field 


4 


Seek complete 


ID Not Found 


3 


Data request 




2 


Data Error 






Corrected 


Aborted Command 


1 


Command in 






progress 


TR000 Error 


LSB 


Error 


DAM Not Found 



COMMAND DESCRIPTIONS 

The BMEC passes on all information between the 
host and the WD1010. Some commands are modified 
by the BMEC and some are simply echoed. The 
following is a list of the commands and their formats 
and descriptions. 



89 



o 

—I. 

© 
45* 



COMMAND 



FORMAT 



DESCRIPTION 



RESTORE 



SEEK 



SCAN ID 



READ SECTOR 



R3 R2 R1 RO 



1 1 R3 R2 R1 RO 



01 000000 



0010DMOE 



WRITE SECTOR 



001 1 0M0E 



READ LONG 



WRITE LONG 



1 1 0D01 E 



01 1 1 D01 E 



WRITE COPY 



1 01 1 M0 E 



Pass on task information and command and initiates a 
read status after the command is completed. The 
command is echoed. Stepping rate (R0-R3) is set. 

Pass on task information and command and initiates a 
read status after the command is completed. The 
command is echoed. Stepping rate (R0-R3) is set. 

Passes command to WD1010 which scans ID headers on 
current track. Updates cylinder number in task file and 
command and initiates a read status after the command 
is completed. The command is echoed. 

Write the buffer with data from WD1010. If ECC is 
enabled, ECC bytes are recomputed by the BMEC. After 
the buffer is full, the recorded ECC bytes are compared 
to the generated bytes to generate the syndrome bytes. 
If the syndrome is non-zero, errors have occurred and 
error correction is invoked by the BMEC. If the error is 
not correctable the BMEC retries the sector read. If the 
data is correctable the BMEC corrects the data and 
passes the data in the buffer to the host. Read status is 
requested by the BMEC and is sent from the WD1010 to 
the host. If, after a specified number of retries, the error 
is still uncorrectable, the BMEC sends an error status to 
the host along wtih the status from the WD1010. 

Write the buffer with data bytes from the host. Pass the 
task information and command to the WD1010. The 
WD1010 seeks track if necessary, then writes the sector 
from the buffer to disk. Generate the ECC polynomial, 
selected by E, as the buffer is written to disc. Write the 
total number of sectors specified by the sector count if 
M = 1 in format. If M =0 then the sector count is ignored 
and only one sector is written. After the sector data is 
written to the disc, the BMEC sends the WD1010 the 
ECC bytes. The BMEC requests status from the WD1010 
and passes on this information to the host at the host's 
request. 

Similar to Read Sector except the ECC operation 
producing a syndrome is inhibited in the BMEC. Instead, 
the BMEC copies the recorded ECC bytes from disc and 
passes them unaltered to the host. 

The Write Long command functions similarly to the Write 
Sector command except the ECC operation of computing 
the ECC word is inhibited in the BMEC. Instead, the BMEC 
accepts a 32, or 56 bit appendage from the host and 
passes it unaltered to the WD1010 to be written on the disc 
after the data. 

The Write Copy command is similar to the Write Sector 
command, except the BMEC does not send a data 
request (DRQ) to the host at the beginning of the 
command. The BMEC assumes it has a full buffer to 
write to the disc. The buffer could have been filled by 
another device other than the host, such as a back-up 
tape or data from another disc. This commands allows 
the copying of data from one disc to another with 
minimal host intervention. 



90 



COMMAND 



READ COPY 



SET PARAMETERS 



FORMAT 



1 01 00M0E 



1 1010000 



DESCRIPTION 



The Read Copy command is similar to the Read Sector 
command, except the BMEC does not send a data 
request (DRQ) to the host at the end of the command. 
This command, when used with the Write Copy com- 
mand, allows the copying of data from one disk to 
another with minimal host intervention. 
The buffer size parameter is specified by the value held in 
the sector size task register. The buffer size corresponds 
to the sector size task register value multiplied by 128. 
(E.G. if the sector size task register value = 1 , then it speci- 
fies a buffer size of 128 bytes. A 32768 (32K) byte length 
buffer is specified by a sector size register value = 0.) 



o 




WD1010 
Winchester 
Controller 




DRIVE 
INTERFACE 



WD1010/WD1014 WINCHESTER CONTROLLER 



See page 725 for ordering information. 



91 



3 

o 

O 
4^ 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



92 



Printed in U S A 



WESTERN DIGITAL 

CORPORAT/ON 

WD1050 SMD Controller/Formatter 




FEATURES 

16 BIT HOST INTERFACE 

9.677 M BITS/SEC DATA RATE 

SINGLE/MULTIPLE SECTOR TRANSFERS 

HARD SECTOR FORMAT 

TTL COMPATIBLE INPUT/OUTPUTS 

SINGLE 5V SUPPLY 

64 PIN JEDEC CHIP CARRIER PACKAGE 

COMPATIBLE WITH SMD, MMD, FHT, LMD, 
AND CMD FAMILIES 



DESCRIPTION 

The WD1050 SMD controller/formatter is a MOS/LSI 
device designed to interface an SMD compatible 
rigid disk drive to a host processor. The device is 
compatible with all rigid disk drives adhering to 
Control Data Corporation's flat cable interface for 
SMD, MMD, FHT, FMD, LMD and CMD families (CDC 
specification 64712400 Rev H). It is TTL compatible 
on all inputs and outputs, with interface capability for 
8 or 16 bit data busses. 

The WD1050 contains a powerful set of macro- 
commands for read/write and control functions. An 
internal 16 bit task file is used to process a selected 
command based upon parameter information in the 
file. 

The WD1050 operates from a single + 5V supply and 
is available in a64 pin JEDEC chip-carrier package. 



O 

cn 

o 




16 



A 
V 



DATA 

I/O 

BUFFER 



A -A 2 Q 

CS — 

RE — 

WE — 

SCS-*- 

BRDY — 
BDRQ «*- 
INTRO.-*- 



3I 



HOST/ 

BUFFER 

CONTROL 



STATUS 



TASK 
FILE 



COMPARATOR 



DATA 



CRC LOGIC 



CONTROL 
UNIT 



CONTROL 
PORT 



^> 



UNITSEL 
PORT 



} 



CPO- 
CP9 



US0- 
US3 



*-»» 



RDS 



RDH 



-RC 



WDH 



WDS 



— RD 



.WD 
-SC 



i~t~v 

-Mi 



DRIVE 

CONTROL 

PORT 



TAG1- 

TAG3 

NDEX 

<• SECTOR 

-* FAULT 

•« SKER 

•4 ONCYL 

-« URDY 

«« WDROT 

-4 UBUSY 

■* USEL 

^USTAG 

*-ECC 



Figure 1 BLOCK DIAGRAM 



93 



PIN 
NUMBER 



PIN NAME 



SYMBOL 



FUNCTION 



vcc 



4 

5-7 
8-23 
24 
25 
26 

27 
28 
29 
30 
31 



32 



33 
34 



35 
36 

37 



READ ENABLE 



WRITE ENABLE 



CHIP SELECT 
ADDRESS 0-*2 
DATA BUS 0-15 
WRITE DATA 
READ CLOCK 
SERVO CLOCK 

READ DATA 
INDEX PULSE 
SECTOR 
UNIT SELECT 
UNIT READY 

UNIT BUSY 



GROUND 
FAULT 



SEEK ERROR 
ON CYLINDER 

WRITE PROTECT 



VCC 
RE 



WE 

CS 

A0-*A2 

D0-D15 

WD 

RC 

SC 

RD 

IP 

SEC 

USEL 

URDY 

UBSY 



VSS 
FAULT 



SKERR 
ONCYL 

WPROT 



+ 5V ± 5% power supply input 

Tri-state bidirectional line, used as an input 
when reading the task file and an output when 
the WD1050 is reading from the buffer. 

Tri-state bidirectional line used as an input 
when writing to the task file and an output when 
the WD1050 is writing to the buffer. _ 

A logic low on this input enables both WE and 
RE signals. 

These three inputs select a task file register to 
receive/transmit data. 

Sixteen bit bidirectional bus used for transfer of 
commands, status, and data. 
Open Drain, NRZ data output which is syn- 
chronized to the Servo Clock input. 

Input clock from the drive which is syn- 
chronized with the Read Data Input. 

A nominal 9.677 MHz clock input from the drive. 
This clock must be valid when Unit Ready (Pin 
31) is active and Fault (Pin 34) is inactive. 

NRZ data input from the drive which must be 
synchronized to the Read Clock (Pin 25) input. 

Active high input used to monitor the Index 

signal from the drive. 

Active high input used to monitor sector pulses 

from the drive. 

Active high output pulse used to strobe US0- 

US2 lines. 

Active high input used to inform the WD1050 of 
a READY condition on a selected drive. If this 
line is made inactive during any command 
(except RTZ or FAULT CLEAR), current com- 
mand execution is terminated. 

Active high input used to monitor drive status 
during a unit selection. If the unit had previously 
been selected and/or reserved prior to issuing a 
USTAG, the UBSY must be made active within 
one microsecond of the USTAG selection. This 
signal is used for dual-channel access ap- 
plications and should be tied to ground when 
not used. 
Ground. 

Active high input used to detect a fault con- 
dition at the drive. Command execution is 
terminated if fault is made active during any 
command. Only the FAULT CLEAR command 
may be issued while this line is ascerted. 

Active high input used to detect a seek error at 
the drive. 

Active high input used to inform the WD1050 
when the heads are settled and positioned over 
the desired cylinder. 

Active high input used to monitor the Write 
Protect signal from the drive. 



94 



PIN 
NUMBER 


PIN NAME 


SYMBOL 


FUNCTION 


38 


ERROR 
CORRECTION 


ECC 


Active high output used to synchronize external 
ECC logic to the Data Field. 


39 


UNIT SELECT TAG 


USTAG 


Active high output used for selection of a unit 
on US0-US3 lines. 


40-42 


TAG1-TAG3 


TAG1-TAG3 


Active high outputs used to strobe specific data 

out on the Control Port Lines. Tag definitions 

are: 

TAG1 — Cylinder address 

TAG2 — Head/Volume select 

TAG3 — Control Tag 








43-46 


UN IT SELECT 0-3 


US0-US3 


These four outputs reflect the contents of the 
unit address field of the task file, and are used 
to select one of four drives. 


47-56 


CONTROL PORT 
BITS 9-0 


CP9-CP0 


Ten bit output bus used to issue tag parameters 
to the selected drive. 


57 
58 


BACK-BIAS 


VBB 
BCS 


Substrate generator. Must be left open by the 
user. 

Active low output used to enable reading or 
writing to the external buffer. 


BUFFER CHIP 
SELECT 


59 


BUFFER COUNTER 
RESET 


BCR 


Active low output that is strobed prior to 
read/write commands. Used to clear an external 
buffer counter. 


60 


BUFFER DATA 
REQUEST 


BDRQ 


This output is set to initiate data transfers 
to/from the external buffer. 


61 


BUFFER READY 


BRDY 


This input informs the WD1050 that the buffer is 
full or empty. 


62 
63 


INTERRUPT 
REQUEST 


INTRQ 
MR 


Active high output which is set at the com- 
pletion of any command, providing the T bit is 
also set in the command word. 

Active low input used to initialize the WD1050, 
usually after a power-up condition. 


MASTER RESET 


64 


CLOCK 


CLK 


2 MHz Master Clock from which all timing is 
derived. 



o 

-J. 

o 
en 

o 



ORGANIZATION 

The Block Diagram of the WD1050 is shown in Figure 
1. Data transfers to and from the host, as well as the 
sector buffer, are transferred via the D0-D15 lines. An 
internal control unit is used to process all commands 
and generate drive control signals in the SMD 
protocol. With the use of an external sector buffer, 
the WD1050 directly transfers data from the buffer to 
the read/write lines by the host/buffer control logic. 
Four buffer control signals are used to manipulate 
the data off-line from the host processor. 



TASK FILE 

Inidividual registers within the task file are acc essed 
via the Ajj-Arj lines in conjunct ion with either Read 
Enable (RE) or Write Enable (WE) signals. Chip Select 
(CS) must also be made active during an RE or WE 
sequence. 

The MSB of the address lines (A2) can be used for 8- 
bit operations when interfacing to 8-bit microproces- 
sors. When A2 = 0, 16 bit programming is in effect as 
shown in Figure 1. When A2 is toggled, 8-bit 
selection is enabled, with data entered on D8-D15 
illustrated in Table 2. 



95 



g 
o 

en 

o 



TABLE 1 TASK FILE (16 BIT PROGRAMMING) 


R/W 


ADDRESS 


TASK FILE REGISTER 


WE 


RE 


A2 


A1 


AO 


D-|5 Da D7 Do 


lS 


v* 











Head Number 


Sector Address 


iS 


is 








1 


Upper Cylinder 


Lower Cylinder 


iS 


lS 





1 





Sector Count 


Section Length/Unit Address 


IS 







1 


1 


Upper Command 


Lower Command 




lS 





1 


1 


Upper Status 


Lower Status 



TABLE 2 TASK FILE (8 BIT PROGRAMMING) 



R 


rw 


ADDRESS 


TASK REGISTER 


WE 


RE 


A2 


A1 


AO 


D7 Do 


lS 


(^ 


1 








Head Number 


is 


iS 











Sector Address 


IS 


\S 


1 





1 


Upper Cylinder 


V* 


K* 








1 


Lower Cylinder 


\S 


lS 


1 







Sector Count 


V* 


^ 










Sector Length/Unit Address 


V* 




1 




1 


Upper Command 


V* 









1 


Lower Command 




V* 


1 




1 


Upper Status 




iS 







1 


Lower Status 



COMMAND SET 

The WD1050 can execute eight macro-commands. 
The appropriate task registers are first loaded with 
parameter information, then the macro-command is 
written into the command register. Table 3 shows the 
eight commands, plus a summary of the various flags 
used to modify the execution of each command. The 
STATUS Register, illustrated in Table 4 allows the 
host to monitor key signals and command progress. 
Note that the status register is a "Read-Only" 



register, while the command register is a "Write 
Only" register. Both these registers share the same 
address, and are differentiated by the ascertion of 
either RE or WE. 

When programmed for the 8-bit mode, two con- 
secutive reads must be accomplished to fetch the 
entire status word from the task file. When A2 = 1, 
status bits D8-D15 are read; when A2 = 0, status bits 
D0-D7 are read. 



COMMAND 


LSB 








COMMAND REGISTER BITS 








MSB 


15 14 


13 


12 


11 


10 9 8 7 6 5 


4 


3 


2 


1 


Fault Clear 














I 





U 


S 


E L 


Return to Zero 








1 


V 


L I 


M 


U 


S 


E L 


Seek Cylinder 





1 





V 


L O I Z C H 


M 


u 


S 


E L 


Read ID Field 





1 


1 





L O I Z C H 


M 


u 


S 


E L 


Read Sector 


1 








R 


L O I Z C H 


M 


u 


s 


E L 


Write Sector 


1 





1 





L O I Z C H 


M 


u 


s 


E L 


Format 


1 


1 








P O I Z C H 


M 


u 


S 


E L 


Verify 


1 


1 


1 





P O I Z C H 


M 


u 


s 


E L 





96 



TABLE 3 COMMAND AND FLAG SUMMARY 



FLAG SUMMARY 


V = Verify 


1 = Interrupt Enable 


R = CRC Enable 


Z = Volume/Head change 


L = Logical Sectoring 


C = Cylinder Addr 


P = Programmable Sectors 


H = Head selection 


= On Cylinder 


M = Marginal data recovery 


E = Priority Release/Early 


U = Unit Sel/Servo Minus 


L = Unit Deselect/Late 


S = Priority Sel/Servo Plus 



o 

O 
CJ1 

o 



TABLE 4 STATUS WORD SUMMARY 





BIT 


STATUS DESCRIPTION 


u 
p 
p 

E 
R 


15 


BUFFER CHIP SELECT STATUS 


14 


COMMAND IN PROGRESS 


13 


UNIT BUSY 


12 


UNIT SELECTED 


11 


WRITE PROTECT 


10 


UNIT READY 


9 


ON CYLINDER 


8 


SEEK ERROR 


L 


W 
E 
R 


7 


BUFFER CHIP SELECT STATUS 


6 


FAULT CONDITION 


5 


BUFFER DATA REQUEST STATUS 


4 


NOT USED 


3 


DATA FIELD CRC ERROR 


2 


DATA SYNCH MARK NOT FOUND 


1 


ID CRC ERROR 





ID NOT FOUND 



FIXED SECTOR FORMAT 



HEAD 


PLO 


SYNC 


ID 


WRITE 


PLO 


SYNC 


DATA 


CRC 


CRC 


END 


END OF 


SCATTER 


SYNC 


CHAR 


FIELD 


SPLICE 


SYNC 


CHAR 




1 


2 


OF 
RECORD 


SECTOR 


16 


11 


1 


6 


2 


11 


1 


128 TO 


1 


1 


2 


7 


BYTES 


BYTES 


BYTE 


BYTES 


BYTES 


BYTES 


BYTE 


1024 BYTES 


BYTE 


BYTE 


BYTES 


BYTES 
(MIN.) 


'00' 


'00' 


'FE' 




'00' 


'00' 


'FE' 








'00' 


'00' 






/ 




— ■ •«_ 

















/ / (All ID Field divisions are 1 byte each) 



UPPER 
CYLADDR 


LOWER 
CYLADDR 


HEAD 


SECTOR 
ADDR 


CRC 

1 


CRC 
2 



See page 725 for ordering information. 



97 



D 

O 

o 



Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital 
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by 
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change 
specifications at anytime without notice. 



98 



Printed in u S <k